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Quiz yourself by thinking what should be in
each of the black spaces below before clicking
on it to display the answer.
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| show | John von Neumannat (the Institute for Advanced Studies, Princeton.)
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| show | software.
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| The processing required for a single instruction is called a(n) | show 🗑
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| show | hardware failure
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| a ___generated by some condition that occurs as a result of an instruction execution. | show 🗑
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| A bus that connects major computer components (processor, memory, I/O) is called a | show 🗑
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| ___ are used to designate the source or destination of the data on the data bus. | show 🗑
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| The data lines provide a path for moving data among system modules and are collectively called the | show 🗑
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| A ___ is the high-level set of rules for exchanging packets of data between devices. | show 🗑
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| show | lane
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| ___receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. | show 🗑
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| show | The QPI routing layer
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| A ___ specifies the address in memory for the next read or write. | show 🗑
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| A ___ contains the data to be written into memory or receives the data read from memory. | show 🗑
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| The most common classes of interrupts are: program, timer, I/O and | show 🗑
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| A(n) ___ is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis. | show 🗑
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| A(n) ___ is generated by an I/O controller to signal normal completion of an operation, request service from the processor, or to signal a variety of error conditions. | show 🗑
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| show | disabled interrupt
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| show | interconnection structure.
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| A ___ is a communication pathway connecting two or more devices. | show 🗑
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| The ___ lines are used to control the access to and the use of the data and address lines. | show 🗑
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| show | power management packets
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| The purpose of the PCIe ___ layer is to ensure reliable delivery of packets across the PCIe link. | show 🗑
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| show | balanced
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| The QPI link layer performs two key functions: flow control and | show 🗑
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| ___is a popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus. | show 🗑
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| show | flow control
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| show | Locality of reference
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| One assertion that locality is based on is that as a function of time, the probability that a given unit of memory is referenced tends to change... | show 🗑
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| ___ location reflects the tendency of a program to access data locations sequentially, such as when processing a table of data. | show 🗑
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| show | temporal
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| show | Spatial
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| show | instruction temporal locality
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| show | data temporal locality
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| show | location
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| show | External
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| show | Unit of transfer
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| show | Sequential access
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| ___ is a random access type of memory that enables one to make a comparison of desired bit locations within a word for a specified match, and to do this for all words simultaneously. | show 🗑
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| show | Access time (latency)
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| show | Main
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| show | Coherence
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| show | processor
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| The principle of ___ reflects the observation that during the course of execution of a program memory references by the processor tend to cluster. | show 🗑
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| Two forms of locality are temporal locality and | show 🗑
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| ___ locality refers to the tendency of a program to reference in the near future those units of memory referenced in the recent past. | show 🗑
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| show | Spatial
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| ___instruction is an instruction that exists in the code to be executed. | show 🗑
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| ___ instruction is instructions that appear in the execution trace of a program. | show 🗑
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| From a user's point of view, the two most important characteristics of memory are capacity and | show 🗑
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| show | Transfer rate
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| show | Memory cycle time
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| External, ___ is referred to as secondary memory or auxiliary memory. | show 🗑
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| show | Coherence
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| show | Locality
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| show | Access time
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| show | Inclusion
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| The ___ cache is slower and typically larger than the L2 cache. | show 🗑
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| ___ is the minimum unit of transfer between cache and main memory. | show 🗑
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| To distinguish between the data transferred and the chunk of physical memory, the term ___ , is sometimes used with reference to caches. | show 🗑
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| ___ is a portion of a cache line that is used for addressing purposes. | show 🗑
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| show | Direct mapping
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| show | thrashing.
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| The principal disadvantage of ___ mapping is the complex circuitry required to examine the tags of all cache lines in parallel. | show 🗑
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| show | least recently used (LRU)
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| show | first-in-first-out (FIFO)
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| show | first-in-first-out (FIFO)
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| The ___ dictates that a piece of data in one cache is guaranteed to be also found in all lower levels of caches. | show 🗑
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| show | exclusive policy
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| show | Fetch/decode unit
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| show | Execution units
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| With ___ additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches. | show 🗑
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| ___memory is designed to combine the memory access time of expensive, high-speed memory combined with the large memory size of less expensive, lower-speed memory. | show 🗑
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| show | Locality of reference
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| show | line size
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| ___ computing deals with supercomputers and their software, especially for scientific applications that involve large amounts of data, vector and matrix computation, and the use of parallel algorithms. | show 🗑
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| show | physical
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| Three mapping techniques that are used for logically organizing cache are direct, ___ , and set-associative. | show 🗑
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| show | Content-addressable memory (CAM)
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| ___ mapping is a compromise that exhibits the strengths of both the direct and associative approaches while reducing their disadvantages. | show 🗑
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| show | Set
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| show | least frequently used (LFU)
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| show | exclusive policy
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| show | Memory subsystem.
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| show | write through
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| show | virtual
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