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J277 1.1.1
Architecture of the CPU
| Term | Definition |
|---|---|
| FDE Cycle | Fetching instructions/data from memory, decoding them into binary and executing the instruction |
| Von Neuman Architecture | Computer system with instructions stored in memory which are fetched by the CPU |
| Arithmetic Logic Unit | Part of the CPU that performs all of the arithmetic and logical functions |
| Accumulator | Stores results of calculations and any data to be used in the calculations by the ALU |
| Control Unit | Part of the CPU that co–ordinates the flow of data within the computer system and executes instructions |
| Register | Fast access part of the processor that stores data being used by the CPU |
| Memory Address Register | CPU component that stores the address of data being accessed in memory. |
| Memory Data Register | Holds the actual data or instruction that has been fetched from memory |
| Program Counter | Holds the memory address of the next instruction to be fetched |
| Components | The devices and parts that make up a computer or device |
| Execution | To run an instruction or set of instructions |