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3150 - Module #3
Microprocessor/Microcontroller
| Question | Answer |
|---|---|
| What's the definition of a microprocessor? | A general purpose computer that's contained in a single integrated circuit (all peripherals are off the CPU chip). It's a CPU on chip. It doesn't have memory, I/O devices, etc. and must be added. |
| What's the definition of a microcontroller? | A microprocessor with a number of integrated peripherals, typically used in control-oriented applications (everything is on one chip). A microcontroller contains a CPU, or multiple, memory, and I/O peripherals. |
| What makes up the general architecture of a microcontroller? | This is the CPU, RAM, ROM, I/O ports (parallel and serial I/O ports), ADC (analog to digital converter and digital to analog converter), Timers, and Interrupt. |
| What's an embedded system? | A computer system with a dedicated functionality within a larger mechanical or electrical system, often with real-time computing constraints. It's embedded as part of a complete device. |
| What're the advantages and disadvantages of embedded systems? | Embedded computers are lower power consumption, smaller size, rugged operating ranges, and lower per-unit cost, but they have limited processing capabilities, resulting in more difficulty when programming with them. |
| What's the definition of the central processing unit? | It monitors and controls all operations performed on the microcontroller. It reads program instructions from ROM memory and executes them. |
| What is an interrupt? | It's a subroutine call that pauses the main operations and causes it to execute any other program, which is more important at the time of operation. When completed, the execution of the main program resumes. |
| Read Only Memory (ROM) or _______ is ________ bytes. | program memory, 4K |
| Random Access Memory (RAM) or ________ is ________ bytes. | data memory, 128 |
| What is an address bus? | It's a 16-bit bus to address memory location. |
| What is a data bus? | It's an 8-bit bus to transfer data. |
| What kind of I/O ports does the Intel 8051 have? | There's four 8-bit parallel I/O ports and one serial I/O port. |
| What pins does port0 make up? Where in memory is port0? | Pins 32 to 39. Port0 is at address 80H. |
| What pins does port1 make up? Where in memory is port1? | Pins 1 to 8. Port1 is at address 90H. |
| What pins does port2 make up? Where in memory is port2? | Pins 21 to 28. Port2 is at address A0H. |
| What pins does port3 make up? Where in memory is port3? | Pins 10 to 17. Port3 is at address B0H. |
| What is the purpose of port0? | It's a dual-purpose port. It's either a general purpose I/O port or a multiplexed address and data bus. |
| What is the purpose of port1? | It's a dedicated I/O port and available to external devices as required. |
| What is the purpose of port2? | It's a dual-purpose port. It's either a general purpose I/O port or the high byte of the address bus for designs with external memory of 64K bytes. |
| What is the purpose of port3? | It's a dual-purpose port. It's either a general purpose I/O port or they're each multi-functional. |
| What does PSEN stand for? Which pin is for the PSEN? What is the purpose of the PSEN? | Program Store Enable (Pin 29) is a control signal that enables external program memory. It's usually connected to an EPROM output enable pin. It's low during a fetch cycle of an instruction stored in external program memory. There's more on slides.*** |
| What does ALE stand for? Which pin is for the ALE? What is the purpose of the ALE? | Address Latch Enable (Pin 30) is for demultiplexing the address and data bus when port 0 is used in its alternate mode. There's more on slides.*** |
| What does EA stand for? Which pin is for the EA? What is the purpose of the EA? | External Access (Pin 31) is generally tied high (+5 volts) or low (ground). If high, programs execute from internal ROM memory. If low, programs execute from external memory only. |
| Which pins are for the On-Chip Oscillator Inputs? What is the purpose of the On-Chip Oscillator Inputs? | These are pins 18 & 19, and they're used for interfacing an external crystal to get the system clock. |
| What does RST stand for? Which pin is for the RST? What is the purpose of the RST? | Reset (Pin 9) is the master RESET. When high for at least two machine cycles, all registers go to default values on a orderly start-up. Normally, RST is low. |
| Which pins are for the Power Connection? What is the purpose of the Power Connection? | These are pins 20 & 40. The Vcc connection (+5V) is on pin 40 and Vss connection (ground) is on pin 20. |
| What are the three groups of RAM memory? | 32 bytes from locations 00H to 1FH are register banks and stack, which are divided into four banks of registers. 16 bytes from locations 20H to 2FH are bit addressable memory. 80 bytes from locations 30H to 7FH are scratch pad memory. |
| How many bit addressable locations does 8051 have? Where are they? | It has 210 bit addressable locations: 128 are at 20H through 2FH and the rest are the special function registers. |
| Why is bit addressability so powerful? | It allows one to set, clear, perform logic operations (AND, OR, etc.), etc. with a single instruction. Otherwise, bit processing would have been done as a sequence of read, modify, and write. |
| 8051 consists of what kind of internal memory? | It has on-chip ROM (program memory) and on-chip RAM (data memory). |
| What does the on-chip RAM contain? | It contains general purpose storage, bit addressable storage, register banks, and special function registers. |
| Where's the stack reside? | It resides in internal RAM. |
| What address is PSW at? What does PSW stand for? What is the purpose of the PSW? | Program Status Word is at address D0H and contains multiple status bits. These include the carry flag, auxiliary carry flag, flag0, register bank select1, register bank select0, overflow flag, even parity flag, and an unused bit. |
| What is the auxiliary carry flag? | It's used when performing BCD operations and is set when there's a carry from the 4th to 5th position upon performing addition. |
| What addresses are banks 0 - 3 located at? | Bank 0 - 00H to 07H Bank 1 - 08H to 1FH Bank 2 - 10H to 17H Bank 3 - 18H to 1FH |
| When is the overflow flag set? More specifically, when does overflow occur? | Overflow flag is set when addition of two positive numbers yields a negative result (or two negatives yield a positive). Alternatively, if you XOR the carry in and carry out and the result is 1, then overflow has occurred. |
| What's a general rule of thumb to remembering the parity bit's purpose? | The number of 1's in the accumulator plus the P bit, whether it's one or zero, is always even. If A = 10101101, P will be 1 because that'd result in four 1's in the accumulator and therefore satisfying even parity. |
| Where's the B register and what's its purpose? | It's at address F0H and is used along with the accumulator for multiplying and dividing. It can also be a general purpose register which is bit addressable through bit addresses F0H to F7H. |
| Explain the inner-workings of the DIV AB and MUL AB operations. | MUL AB stores the 16 bit result in A (low-byte) and B (high-byte). DIV AB leaves the quotient in A and the remainder in B. |
| Where's the stack pointer, and what does it do? | It's at address 81H, an 8-bit register, and contains the address of the data item currently on top of the stack. |
| What's the default value of the stack pointer, and what's the first location used by the stack? | The default value of the stack pointer is 07H, and the first location used by the stack is RAM location 08H. |
| Where's the stack located? How do you access it? | The stack is located in internal RAM (the first 128 bytes of on-chip RAM) and is limited to addresses accessible by indirect addressing. Push and pop are the available stack operations. |
| What happens when you push and pop the stack? | Pushing an item to the stack increments the SP before writing the data to the stack, and popping from the stack reads the data and then decrements the SP. This limits the stack to 32 bytes. |
| What would the instruction be if we wanted to have the stack beginning at 60H? | MOV SP, #5FH This is because of the auto-increment feature of the SP when pushing to the stack. |
| What address locations can stack be used at? What if we need more memory? | Locations 08H to 1FH can be used for the stack. If that's full, we can use locations 30H to 7FH (keep in mind, you must set the stack pointer to 29H first). |
| Where's the DPTR located at? What's the DPTR used for? | It's located at 82H and 83H, and it's a 16-bit register with 82H being DPL (low-byte) and 83H being DPH (high-byte). In other words, you can use DPH, DPL or DPTR. The DPTR is used to access external code or external data memory. |
| What's unique about P1.2 and P1.7? | They're always available as general purpose I/O lines. |
| How many timers/counters are there in 8051? What're their names? | 8051 has two 16-bit timers/counters for timing intervals or counting events. They're called Timer 0 and Timer 1. |
| Where are the timers/counters in 8051 located? Explain in detail. | Timer 0 is at address 8AH (TL0, low-byte) and 8CH (TL0, high-byte). Timer 1 is at address 8BH (TL1, low-byte) and 8DH (TL1, high-byte). |
| What're the time operation registers in 8051? Where are they located? | Time operation is set by TMOD (timer mode register) and TCON (timer control register). TMOD is at address 89H, and TCON is at address 88H. |
| Is TCON bit-addressable? | Yes. |
| Is TMOD bit-addressable? | No, only TCON is bit-addressable. |
| What does SBUF stand for? Where is SBUF located? What does SBUF do? | SBUF is the serial data buffer at address 99H. 8051 has an on-chip serial port for communication with serial devices. SBUF is a serial port register that holds both the transmitting and receiving data. |
| What are the interrupt registers of 8051? What does each do specifically? | 8051 has a 5-source, 2 priority level interrupt structure. Interrupts are enabled by writing to the interrupt enable register (IE). The priority level of an interrupt is set through the interrupt priority register (IP). |
| Where are IP and IE located in 8051? | IP is located at address B8H and IE is located at address A8H. |
| Is the interrupt priority register (IP) bit-addressable? | Yes. |
| Is the interrupt enable register (IE) bit-addressable? | Yes. |
| What is PCON's purpose? What does PCON stand for? Where is it located? | PCON stands for power control register at address 87H. It contains different control bits not specified here. |
| What 16-bit registers exist in 8051? | These are the timer registers, program counter, and data pointer. |
| When external memory is used, what port is unavailable as an I/O port? Why? | Port0 is unavailable because it becomes a multiplexed address bus (A0-A7) and data bus (D0-D7) with ALE latching the low-byte of the address at the beginning of each external memory cycle. |
| When external memory is used, what port is usually (but not always) used for the high-byte of the address bus? | Port2 normally serves this purpose (but not always). |
| How is external ROM enabled? (Accessing External Code Memory) | It's enabled by the PSEN signal. |
| When an external EPROM is used, what happens? (Accessing External Code Memory) | When this happens, port0 and port2 become unavailable as general purpose I/O ports. |
| What happens during the first half of the memory cycle? (Accessing External Code Memory) | During the first half, the low-byte of the address is provided on port0 and is latched using ALE. |
| What happens during the second half of the memory cycle? (Accessing External Code Memory) | During the second half, port0 is used as the data bus and data is read or written depending on the operation. |
| During a typical machine cycle, _______ pulses ______ and _____ bytes are ______ from ______ memory. (Accessing External Code Memory) | ALE, twice, 2, read, program. |
| How do we access external data memory, instruction wise? | The only way to access external data memory is to use the MOVX instruction with the 16-bit data pointer, R0, or R1 as the address register. |
| How do you enable external data memory? | To enable the external data memory, you use RD and WR. RD is the alternate pin function for P3.7 and WR is P3.6's alternate pin function. |
| 8-bit addresses can access how much RAM? What if we need to access even more RAM? (Accessing External Data Memory) | It can access a 256-byte page of RAM. If more than one page of RAM is used/needed, then a few bits from port2 can be used to select that page. |
| What is DAM, RAM, and SAM? | DAM - Direct Access Memory (partially mechanic, partially electronic) RAM - Random Access Memory (purely electronic memory) SAM - Sequential Access Memory (purely mechanic memory) |
| Which is faster? Which is slowest? What memory is used for each? | SAM is like tape, it's slow since you must go through all other data/addresses for some values (SAM is slowest). DAM is like a record player, it's slow to get the head pointed to the address, mechanically, but faster than SAM. RAM is fastest. |
| RAM is ________ and ________ memory, ROM is _______ ________ memory. | read write, read only |
| Why is RAM even used if ROM is cheaper? | ROM is read only memory while RAM is read and write memory. ROM is cheaper and faster but has limited functions. ROM can't decipher program context either. RAM is more expensive and slower but essential to instructions. |
| What is unique about port0 and port2? | They can combine to form a 16-bit address memory (register). |
| Stack is on ________ RAM, not _________ RAM | Internal RAM, On-Chip RAM |
| Which is the better instruction to use? MOV A, R5 or MOV A, 05H | Although they both mean the same, you'd use MOV A, R5 because it's only a 1 byte instruction while the other is a 2 byte instruction. |
| True or False? A microprocessor is a special purpose processor that's constrained in a single chip including a number of integrated peripherals. | False. |
| True or False? On reboot of the 8051, the program counter (PC) is initialized as 0000H. | True. |
| True or False? An embedded system is a general purpose computer. | False. |
| True or False? Input/output ports are accessible like any other memory location. | True. |
| True or False? R0 - R7 are bit addressable. | False. |
| True or False? The default value of the stack pointer is 07H. | True. |
| True or False? Port1 is a dual-purpose port. | False. |
| True or False? DPTR is a 16-bit register that's also accessible in low-byte and high-byte formats. | True. |
| True or False? The serial data buffer register just holds the transmit data. | False. |
| True or False? Interrupt Enable register and Interrupt Priority register are not bit addressable. | False. |
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bmcisme
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