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Ch. 4 Terms
| Term | Definition |
|---|---|
| buffer overflow attack | Malicious software that attempts to run its code from an area of memory assigned to another program. |
| CAS Latency | A method of measuring access timing to memory, which is the number of clock cycles required to write or read a column of data off a memory module. CAS stands for Column Access Strobe. |
| Centrino | A technology used by Intel whereby the processor, chipset, and wireless network adapter are all interconnected as a unit, which improves laptop performance. |
| DDR | A type of memory technology used on DIMMs that runs at twice the speed of the system clock, has one notch, and uses 184 pins. Also called DDR SDRAM, SDRAM II, and DDR. |
| DDR2 | Memory that is faster and uses less power than DDR. |
| DDR3 | Memory that is faster and uses less power than DDR2. |
| DDR3L | Memory that is faster and uses less power than regular DDR3. |
| DDR4 | Memory that is faster and uses less power than DDR3. |
| DIMM (dual inline memory module) | A miniature circuit board installed on a motherboard to hold memory. |
| Double Data Rate SDRAM (DDR SDRAM) | A type of memory technology used on DIMMs that runs at twice the speed of the system clock, has one notch, and uses 184 pins. Also called DDR SDRAM, SDRAM II, and DDR. |
| double-sided | A DIMM feature whereby memory chips are installed on both sides of a DIMM. |
| dual channels | A motherboard feature that improves memory performance by providing two 64-bit channels between memory and the chipset. DDR, DDR2, DDR3, and DDR4 DIMMs can use dual channels. |
| dual processors | Two processor sockets on a server motherboard. |
| dual ranked | Double-sided DIMMs that provide two 64-bit banks. The memory controller accesses first one bank and then the other. Dual-ranked DIMMs do not perform as well as single-ranked DIMMs. |
| dynamic RAM (DRAM) | The most common type of system memory, it requires refreshing every few milliseconds. |
| ECC (error-correcting code) | A chipset feature on a motherboard that checks the integrity of data stored on DIMMs or RIMMs and can correct single-bit errors in a byte. More advanced ECC schemas can detect, but not correct, double-bit errors in a byte. |
| Execute Disable Bit (EDB) | A processor security feature that can work with the operating system to designate an area of memory for holding data or instructions. |
| graphic processing unit (GPU) | A processor that manipulates graphic data to form the images on a monitor screen. A GPU can be embedded on a video card, on the motherboard, or integrated within the processor. |
| Hyper-Threading | The Intel technology that allows each logical processor within the processor package to handle an individual thread in parallel with other threads being handled by other processors within the package/ |
| Hyper Transport | The AMD technology that allows each logical processor within the processor package to handle an individual thread in parallel with other threads being handled by other processors within the package. |
| Level 1 cache (L1 cache) | Memory on the processor die used as a cache to improve processor performance. |
| Level 2 cache (L2 cache) | Memory in the processor package but not on the processor die. The memory is used as a cache or buffer to improve processor performance. |
| Level 3 cache (L3 cache) | Cache memory further from the processor core than Level 2 cache but still in the processor package. |
| memory bank | The memory a processor addresses at one time. Today's desktop and laptop processors use a memory bank that is 64 bits wide. |
| multicore processing | A processor technology whereby the processor housing contains two or more processor cores that operate at the same frequency but independently of each other. |
| multiplier | The factor by which the bus speed or frequency is multiplied to get the CPU clock speed. |
| multiprocessing | Two processing units installed within a single processor and first used by the Pentium processor. |
| multiprocessor platform | A system that contains more than one processor. The motherboard has more than one processor socket and the processors must be rated to work in this multiprocessor environment |
| parity | An older error-checking scheme used with SIMMs in which a ninth, or "parity," bit is added. The value of the parity bit is set to either 0 or 1 to provide an even number of 1s for even parity and an odd number of 1s for odd parity. |
| parity error | An error that occurs in parity error checking when the number of 1s in the byte is not in agreement with the expected number. |
| processor frequency | The speed at which the processor operates internally. Usually expressed in GHz. |
| quad channels | Technology used by a motherboard and DIMMs that allows the memory controller to access four DIMMS at the same time. DDR3 and DDR4 DIMMs can use quad channels. |
| RAS Latency | A method of measuring access timing to memory, which is the number of clock cycles required to write or read a row of data off a memory module. RAS stands for Row Access Strobe. |
| RIMM | An older type of memory module developed by Rambus, Inc. |
| SDRAM II | A type of memory technology used on DIMMs that runs at twice the speed of the system clock, has one notch, and uses 184 pins. Also called DDR SDRAM, SDRAM II, and DDR. |
| SIMM (single inline memory module) | An outdated miniature circuit board used to hold RAM. SIMMs held 8, 16, 32, or 64 MB on a single module. SIMMs have been replaced by DIMMs. |
| single channel | The memory controller on a motherboard that can access only one DIMM at a time. Compare with dual channels and triple channels. |
| single-sided | A DIMM that has memory chips installed on one side of the module. |
| SO-DIMM (small outline DIMM) | A type of memory module used in laptop computers that uses DIMM technology. A DDR3 SO-DIMM has 204 pins. A DDR2 or DDR SO-DIMM has 200 pins. Older, outdated SO-DIMMs can have 72 pins or 144 pins. |
| static RAM | RAM chips that retain information without the need for refreshing, as long as the computer's power is on. They are more expensive than traditional DRAM. |
| synchronous DRAM (SDRAM) | The first DIMM to run synchronized with the system clock that has two notches, and uses 168 pins. |
| thermal compound | A creamlike substance that is placed between the bottom of the cooler heat sink and the top of the processor to eliminate air pockets and to help to draw heat off the processor. |
| thread | Each process that the processor is aware of; a single task that is part of a longer task or request from a program. |
| triple channels | When the memory controller accesses three DIMMs at the same time. DDR3 DIMMs support triple channeling. |
| x86 processor | An older processor that first used the number 86 in the model number and processes 32 bits at a time. |
| x86-64 processor | Hybrid processors that can process 32 bits or 64 bits. |
Created by:
drewtang40
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