click below
click below
Normal Size Small Size show me how
Ch7-St2
| Question | Answer |
|---|---|
| General Protection Fault (GPF) | in the Intel x86 and AMD x86-64 architectures, and other unrelated architectures, is a fault gpf |
| memory bank | is a logical unit of storage in electronics, which is hardware dependent. In a computer the memory bank may be determined by the memory bank |
| parity | a symmetry property of physical quantities or processes under spatial inversion parity |
| parity error | checking is the storing of a redundant parity bit representing the parity (odd or even) of a small amount of computer data (typically one byte) stored in random access memory, and the subsequent comparison of the stored parity error |
| re-marked chips | is the chip manufacturer and who is the module manufacturer remarked chip |
| RIMM | is a memory module developed by Kingston Technology Corp. that takes up less space inside the computer than the older DIMM module and has different pin characteristics rimm |
| SIMM (single inline memory module) | is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s simm |
| Single channel | this is used on broadcast satellites to indicate that radio stations are not multiplexed as subcarriers onto a single video carrier, but instead independently share a transponder single channel |
| single ranked | is a set of DRAMs connected to the same chip select, and which are therefore accessed simultaneously single ranked |
| single-sided | is a type of random-access memory module which has its chips divided into two sides (called ranks), only one of which can be addressed at a time by the computer single sided |
| SO-DIMM (small outline DIMM) | is a type of computer memory built using integrated circuits so dimm |
| synchronous DRAM (SDRAM) | is dynamic random access memory (DRAM) that is synchronized with the system bus sdram |
| triple channels | is a technology that increases the transfer speed of data between the DRAM memory and the chipset memory controller by adding more channels of communication between them triple channels |