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pm-ch6-stack1
| Term | Definition |
|---|---|
| Advanced Configuration and Power Interface (ACPI) | Specification developed by Intel, Compaq, Phoenix, Microsoft, and Toshiba to control power on computers and other devices. |
| back-side bus (BSB) | The portion of a processor's internal bus that connects the processor to the internal memory cache. The bus operates at a much higher frequency than the front side bus. |
| case fan | A fan inside a computer case used to draw air out or into the case. |
| Centrino | A technology used by Intel whereby the processor, chipset, and wireless network adapter are all connected as a unit which improves laptop performance. |
| chassis air guide (CAG) | A round air duct that helps to pull and direct fresh air from outside a computer case to the cooler and processor |
| Cool’n’Quiet | A feature of AMD processors that lower power requirements and helps keep a system quiet. |
| Cooler | A combination cooling fan and heat sink mounted on the top or side of the processor to keep it cool. |
| DRAM | The most common type of system memory, it requires refreshing every few milliseconds. |
| dual-core processing | A processor package that contains two core processors, thus supporting four instructions at once |
| Enhanced Intel SpeedStep Technology (EIST) | A processor feature used by Intel that steps down processor frequency when the processor is idle to conserve power and lower heat. |
| Execute disable bit | A processor security feature by Intel that preserves software from executing or reproducing itself if it appears to be malicious |
| front-side bus (FSB) | The bus between the CPU and memory on the motherboard. The bus frequency in documention is called the system speed, such as 400mhz. Also called the memory bus, front-side bus, local bus, or host bus. |
| heat sink | A piece of metal, with cooling fans, that can be attached or mounted on an integrated chip to disparate heat. |
| hyper-threading | The Intel technology that allows each logical processor within the processor package to handle an individual thread parallel with other threads being handled by other processors within the package |
| hyper transport | The AMD technology that allows each logical processor within the processor package to handle an individual thread parallel with other threads being handled by other processors within the package |
| internal bus | The bus inside the CPU that is used for communication between the CPU's internal components. |
| Level 1 (L1) cache | Memory on the processor die used as a cache to improve processor performance. |
| Level 2 (L2) cache | Memory inn the processor package, but not on the processor die. The memory is used as a cache or buffer to improve processor performance |
Created by:
pat20141720
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