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np-ch6-stack1
| Question | Answer |
|---|---|
| Advanced Configuration and Power Interface (ACPI) | Specification developed by Intel, Compaq, Phoenix, Microsoft, and Toshiba to control power on computers and other devices |
| back-side bus (BSB) | The portion of the internal bus that connects the processor to the internal memory cache |
| case fan | A fan inside a computer case used to draw air out of or into the case |
| Centrino | A technology used by Intel whereby the processor, chipset, and wireless network adapter are all interconnected as a unit which improves laptop performance |
| chassis air guide (CAG) | A round air duct that helps to pull and direct fresh air from outside a computer case to the cooler and processor |
| Cool’n’Quiet | A feature of AMD processors that lowers power requirements and helps keep a system quiet |
| Cooler | A combination cooling fan and heat sink mounted on the top or side of a processor to keep it cool |
| DRAM | The most common type of system memory, it requires refreshing every few milliseconds. |
| dual-core processing | A processor package that contains two processors, thus supporting four instructions at once |
| Enhanced Intel SpeedStep Technology (EIST) | A processor feature used by Intel that steps down processor frequency when the processor is idle to conserve power and lower heat |
| Execute disable bit | A processor security feature by Intel that prevents software from executing or reproducing itself if it appears to be malicious |
| front-side bus (FSB) | The bus between the CPU and memory on the motherboard. |
| heat sink | A piece of metal,with cooling fins, that can be attached to or mounted on an integrated chip to dissipate heat. |
| hyper-threading | The intel technology that allows each logical processor within the processor package to handle an individual thread in parallel with other threads being handled by other processors within the package |
| hyper transport | The AMD technology that allows each logical processor within the processor package to handle an individual thread in parallel with other threads being handled by other processors within the package |
| internal bus | The bus inside the CPU that is used for communication between the CPU's internal components |
| Level 1 (L1) cache | Memory on the processor die used as a cache to improve processor performance. |
| Level 2 (L2) cache | Memory in the processor package, but not on the processor die |
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npelbano
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