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Quiz 3

Alexsander Milenkovic

QuestionAnswer
Interrupts can be triggered by external or internal (relative to the CPU core) hardware events and may occur at unpredictable times (i.e., they are typically asynchronous to program execution). TRUE
During exception processing, the program counter (PC) and the status register (SR) are both pushed on the stack. TRUE
Interrupts cannot be triggered from software (e.g., by setting a flag bit by the BIS instruction). FALSE
The GIE bit in the status register is cleared when an interrupt is accepted during the exception processing. TRUE
When multiple interrupt requests are pending at the same time, the MSP430 will first serve the longest pending one (i.e, the one that arrived first). FALSE
An interrupt service routine for a serial communication device can return an output parameter as shown below. #pragma vector=USART1RX_VECTOR __interrupt char usart1_rx () {...} FALSE
Interrupts can be triggered by external or internal hardware events and may occur at unpredictable times (i.e., asynchronous to program execution). TRUE
During exception processing only status register (SR) is pushed on the stack. FALSE
Interrupts can be triggered from software (e.g., by setting a flag bit). TRUE
By default the GIE bit in the status register is cleared when an interrupt is accepted during exception processing. TRUE
Interrupt vector table is located in flash memory at known address. TRUE
When multiple interrupt requests are pending at the same time, the MSP430 accepts the longest pending one (i.e, the one that arrived first). FALSE
Interrupts coming from ports P1 and P2 can be enabled or disabled at any time in software. TRUE
An interrupt enable bit associated with a peripheral is always automatically cleared upon accepting the corresponding interrupt request. FALSE
During an instruction execution an interrupt request from a communication device arises. The MSP430 will accept this request if no other requests are pending and the global interrupt enable is cleared, GIE=0. FALSE
The MSP430 cannot handle interrupt requests that arise outside the chip. FALSE
When multiple interrupt requests are pending at the same time, the MSP430 accepts the one that arrived first (earliest in time). FALSE
Each entry in the interrupt vector table contains the starting address of the corresponding interrupt service routine. TRUE
Nesting of interrupt service routines by default is disabled in MSP430 because the GIE bit is cleared during exception processing. TRUE
Interrupts can be triggered from software (e.g., by setting a flag bit). TRUE
Interrupts typically arise asynchronously to program execution. TRUE
What is the size of the interrupt vector table in bytes for an MSP430 that has 32 entries in the interrupt vector table? Each entry contains the starting address of the corresponding interrupt service routine, which is 2 bytes. The total size is 32*2=64 bytes
Where is the interrupt vector table from 2.A located (give the address range)? The interrupt vector table resides at the top of 64KB address space – the highest interrupt vector entry resides at the address @0xFFFE (RESET vector). If we have 32 entries the IVT occupies 0xFFC0 – 0xFFFE.
What is the last instruction in an ISR (Interrupt Service Routine) and what does it do? The last instruction is RETI – return from interrupt. It retrieves the status register and the program counter from the stack.
How many external interrupts (those that originate outside the MSP chip) an MSP430 could serve? How many ISRs are devoted to handling such interrupts? 16 and 2 (2 parallel ports x 8 request lines max = 16 requests, 2 service routines)
List registers used to record interrupt requests: IFG1, IFG2, P1.IFG, P2.IFG
List registers used to support selective masking of interrupts: IE1, IE2, P1.IE, P2.IE
What does the instruction RETI do? 1. Retrieves the status register from the stack. 2. Retrieves the program counter from the stack.
What is the purpose of the GIE bit? Where is it located? Serves to mask all maskable interrupts. It is located in the status register (R2).
What registers are pushed onto the stack during exception processing and popped from the stack during execution of the RETI instruction? Program counter and the status register (PC and SR).
How does the interrupt vector table get initialized? It is initialized by software developers (in case of assembly) or compiler (in case of C) by storing the starting addresses of interrupt service routines into the corresponding entries of the Interrupt Vector Table.
What steps need to be taken in interrupt service routines that serve multi-source requests? In case of multi-source interrupts, the interrupt service routine needs to handle individual requests and to clear the interrupt flag bits explicitly.
Two peripherals P1 and P2 request interrupts at the same time. The ISR_P1 has its starting address in the entry #9 of the interrupt vector table, and ISR_P2 has its starting address in entry #6 of the interrupt vector table. Which request serviced 1st? ISR_P1
Created by: evinsmc