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ECE437 Module 7

Flashcards for Module 7

Consider a logical address with 18 bits used to represent an entry in a conventional page table. How many entries are in the conventional page table? 262144
A(n) ______ matches the process with each entry in the TLB address-space identifier
Assume a system has a TLB hit ratio of 90%. It requires 15 nanoseconds to access the TLB, and 85 nanoseconds to access main memory. What is the effective memory access time in nanoseconds for this system? 108.5
The _____ is an approximation of a program's locality. working set
The mapping of a logical address to a physical address is done in hardware by the ________. Memory management unit (MMU)
An address generated by a CPU is referred to as a ____. logical address
Without a mechanism such as an address-space identifier, the TLB must be flushed during a context switch. True
A page fault must be preceded by a TLB miss True
Inverted page tables require each process to have its own page table False
A 32-bit logical address with 8 KB page size will have 1,000,000 entries in a conventional page table. False
Belady's anomaly states that... for some page replacement algorithms, the page-fault rate may increase as the number of allocated frames increases
Optimal page replacement ____. is used mostly for comparison with other page-replacement schemes
Given the reference string of page accesses: 1 2 3 4 2 3 4 1 2 1 1 3 1 4 and a system with three page frames, using the LRU replacement algorithm, what is the number of page faults for the given reference string? 8
_____ is the dynamic storage-allocation algorithm which results in the smallest leftover hole in memory. Best fit
Absolute code can be generated for... compile-time building
Suppose a program is operating with execution-time binding and the physical address generated is 300. The relocation register is set to 100. What is the corresponding logical address? 200
Consider a 32-bit address for a two-level paging system with an 8KB page size. The outer page table has 1024 entries. How many bits are used to represent the second-level page table? 9
Consider a logic address with a page size of 8KB. How many bits must be used to represent the page offset in the logical address? 13
A(n) ___ page table has one page entry for each real page (or frame) of memory inverted
In the enhanced second change algorithm, which of the following order pairs (r,m) represents a page that would be the best choice for replacement? (0,0)
___ is the dynamic storage-allocation which results in the largest leftover hold in memory. Worst fit
Stack algorithms can never exhibit Belady's anomaly True
A page fault must be preceeded by a TLB miss True
On a system with demand-paging, a process will experience a high page fault rate when the process just begins execution True
___ occurs when a process spends more time paging than executing Thrashing
The ___ allocation algorithm allocates available memory to each process according to its size proportional
Which of the following is true of compaction? It is possible only if relocation is dynamic and done at execution time
Suppose we have file access: 1 2 3 4 2 3 4 1 2 1 1 3 1 4 and there are 3 frames within our system. Using FIFO, what is the number of page faults for the given reference string? 8
Given the logical address 0xAEF9 with a page size of 256 bytes, what is the page offset? 0xF9
Dynamic load register... A stub is included in the image for each library-routine reference
There is a 1:1 correspondence between the number of entries in the TLB and the number of entries in the page table. False
___ is the algorithm implemented on most systems Least-Recently Used
Given the logical address 0xAEF9 with a page size of 256 bytes, what is the page number? 0xAE
Given reference string 1 2 3 4 2 3 4 1 2 1 1 3 1 4 and a system with three page frames, what is the final configuration of the 3 page frames after the true LRU algorithm is applied? 3,1,4
What size segment will be allocated for a 39KB request on a system using the Buddy system for kernel memory allocation? 64KB
Created by: ecmartz
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