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comp arch
| Question | Answer |
|---|---|
| TLB stands for | Translation Lookaside Buffer |
| LRU stands for | Least Recently Used |
| LUT stands for | Look-Up Table |
| FWFT stands for | First Word Falls Through |
| BRAM stands for | Block RAM |
| CLB stands for | Configurable Logic Block |
| What is the process of loading configuration into an FPGA when it powers on | Configuration |
| What are the three types of pipeline hazards | Data hazard, Control hazard, Structural hazard |
| Data hazard definition | When an instruction needs a value that a previous instruction hasn't finished producing yet |
| Control hazard definition | When the pipeline fetches instructions after a branch before it knows whether the branch is taken or not |
| Structural hazard definition | When two instructions need the same hardware resource at the same time |
| What is forwarding | A shortcut that grabs a result from a pipeline register and routes it directly to the EX stage input instead of waiting for write back |
| What is a bubble | A NOP instruction inserted into the pipeline to stall an instruction and buy time for the previous one to produce its result |
| What hazard cannot be fixed with forwarding alone | Load-use hazard |
| Load-use hazard definition | When a lw is immediately followed by an instruction that uses the loaded value |
| How many bubbles does a load-use hazard need | One bubble plus a forward from MEM/WB |
| What is dynamic branch prediction | A scheme that uses a finite state machine to track branch behavior at runtime to guess whether a branch will be taken |
| What happens when a branch prediction is wrong | The speculatively fetched instructions are flushed and the PC is restored to the correct address |
| Vectored interrupt definition | Each exception type has its own handler address in a table and the hardware jumps directly to the right one |
| Non-vectored interrupt definition | All exceptions jump to one fixed address and software figures out what caused it |
| What is clock skew | The difference in arrival time of the same clock edge at different registers due to different wire lengths |
| What is a clock domain | A region of a chip where all registers are driven by the same clock signal |
| Setup time definition | The minimum time data must be stable at a register input BEFORE the capture clock edge |
| Hold time definition | The minimum time data must remain stable at a register input AFTER the capture clock edge |
| Setup slack | The margin by which the setup timing requirement is met. Positive is good |
| Hold slack | The margin by which the hold timing requirement is met. Positive is good |
| If clock reaches REG2 earlier than REG1 what happens to setup slack | Setup slack decreases because the capture edge arrives sooner giving data less time to arrive |
| What is a LUT | A small SRAM-based truth table that implements any combinational logic function by storing one output per input combination |
| What is fracturability | The ability of a single LUT to be split into two or more independent smaller LUTs each implementing a separate function |
| What is a connection box | A programmable structure that connects CLB pins to the wires in the routing channel |
| What is a switch box | A programmable structure at the intersection of routing channels that controls which wires can connect across channels |
| What does topology refer to in FPGA routing | The specific pattern of which connections are possible in a switch box |
| What does flexibility refer to in FPGA routing | The number of connections that can be made in a connection or switch box |
| What is a clock tree | A balanced hierarchical distribution network that delivers the clock to all registers with equal delay to minimize clock skew |
| True dual-port BRAM allows which simultaneous operations | Simultaneous reading from the same address and simultaneous writing to different addresses |
| FIFO two NEVER rules | Never write to a full FIFO and never read from an empty FIFO |
| Almost Empty flag advantage over Empty flag | Gives advance warning so downstream logic can prepare to stop reading before the FIFO actually goes empty |
| What is a page fault | When a required page is not in RAM and must be loaded from disk |
| What is the page number in a virtual address | The upper bits of the address after stripping off the bottom log2 of page size bits |
| TLB hit definition | The required page translation is found in the TLB |
| TLB miss definition | The translation is not in the TLB and the page table must be checked |
| What are the five pipeline stages | IF Instruction Fetch, ID Instruction Decode, EX Execute, MEM Memory Access, WB Write Back |
| What do pipeline registers do | Hold data in transit between pipeline stages so multiple instructions can be in different stages simultaneously |
| Launch edge definition | The clock edge that loads data into the source register and starts it propagating toward the destination |
| Capture edge definition | The clock edge that loads the propagated data into the destination register |
| What is direct mapping in cache | Each block from main memory maps to exactly one specific cache slot based on its block ID |
| What is set associative cache | Cache is divided into sets each holding multiple blocks so a memory block can go into any slot within its set |
| Disadvantage of set associative vs direct mapped cache | Requires comparing multiple tags simultaneously making lookup slower and requiring more hardware |
| Address decomposition order MSB to LSB | Tag then Block ID then Byte Offset |
| Block size formula | 2 to the power of offset bits |
| Number of blocks in main memory formula | 2 to the power of block ID bits |
| What is static power | Power consumed just by being on even with no activity due to transistor leakage |
| What is dynamic power | Power that depends on activity voltage squared and clock rate |
Created by:
anisa-13