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New Digital Circuit
| Question | Answer |
|---|---|
| What is the process to convert an FSM to a controller (HW7 3.39 3.40 3.41)? | 1. Encode states with binary bits. 2. Build state transition truth table (current state bits + inputs = rows, next state bits + outputs = columns). 3. Minimize each next-state and output equation using K-maps. 4. Implement with a state register (D flip-fl |
| How do you assign state encodings when converting FSM to controller (HW7 3.39)? | Assign binary codes to each state. N states need ceil(log2(N)) flip-flops. Example: 4 states A B C D get encodings 00 01 10 11. The encoding choice affects the complexity of next-state equations. |
| How do you fill the state transition truth table for Figure 3.109 FSM (HW7 3.39)? | Rows are all combinations of s1 s0 and input a. For each row look up the current state in the FSM diagram find the transition taken given that input and write the next state encoding and output y. States A=00 B=01 C=10 D=11. |
| What are the output equations for Figure 3.109 FSM controller (HW7 3.39)? | y=0 in states A(00) and D(11). y=1 in states B(01) and C(10). So y = s1 XOR s0 (output is 1 when exactly one state bit is 1). |
| What are the next-state equations for Figure 3.109 FSM (HW7 3.39)? | From state A(00): if a=1 stay A, if a=0 go B(01). From B(01): if a=1 go C(10), if a=0 stay B. From C(10): if a=1 go D(11), if a=0 go B(01). From D(11): always go A(00). Derive n1 n0 by K-map from these transitions. |
| What is the state transition truth table size for Figure 3.110 FSM with inputs a and b (HW7 3.40)? | 4 states need 2 state bits. 2 inputs a and b. Total input columns = s1 s0 a b = 4 bits. Truth table has 2-to-the-4 = 16 rows with outputs n1 n0 and y. |
| What is the controller design for FSM where Y=1 for two clock cycles after X rises (HW7 3.41)? | Three states: S0=00 (Y=0 waiting for X rise), S1=01 (Y=1 first cycle), S2=10 (Y=1 second cycle). Need to detect X rising edge so add a state for X=0 waiting. Truth table has s1 s0 X as inputs. n1=s0, n0=s1-complement AND s0-complement AND X, y=s1 OR s0. |
| What is the controller FSM for Y=1 for five cycles after X rises (HW7 3.45)? | Seven states: S0(Y=0 wait X=0), S1(Y=0 wait X=1 detected), S2 through S6(Y=1 cycles 1-5). After S6 return to S0. Need 3 flip-flops (ceil log2 of 7 = 3). Y=1 in states S2 through S6. |
| How do you reverse engineer a sequential circuit to find its FSM (HW7 3.48)? | Step 1: identify state register bits (s1 s0). Step 2: write Boolean equations for each next-state bit (n1 n0) from the combinational gate logic. Step 3: write output equation y. Step 4: evaluate equations for all state+input combinations to build truth ta |
| What are the next-state equations for Figure 3.113 sequential circuit (HW7 3.48)? | From the gate circuit: identify each gate connected to D inputs of the state register flip-flops. Trace the logic from s1 s0 and input a through AND OR NOT gates to get n1 and n0 as Boolean expressions. Then evaluate for all 8 combinations of s1 s0 a. |
| How do you build the truth table when reverse engineering Figure 3.113 (HW7 3.48)? | List all combinations of s1 s0 and input a (8 rows total). For each row substitute values into your n1 n0 and y equations and compute the result. Each row shows current state + input → next state + output. |
| How do you draw the FSM from a reverse-engineered truth table (HW7 3.48)? | Group rows by current state (s1 s0 value). For each state create a circle. For each row draw a transition arrow to the next state (n1 n0) labeled with the input condition and output. States with same output can be identified as Moore outputs inside circle |
| What is glitching in a controller and how do registered outputs fix it (HW7 3.52)? | Glitching: combinational output logic produces temporary wrong values right after a clock edge while signals settle through different delay paths. Fix: add D flip-flops at each output. Outputs only change on clock edges after logic has fully settled. Trad |
| How do you calculate the glitch timing for Figure 3.68 with AND=2ns and inverter=1ns (HW7 3.52)? | z=s1-complement: appears after 1ns. w=s1: appears after 0ns (direct). x=s1 AND s0-complement: 1ns invert + 2ns AND = 3ns. y=s1-complement AND s0: 1ns + 2ns = 3ns. Between clock edge and 3ns temporary wrong values may appear on x and y. |
| What is a 4-bit up-counter with cnt and clear built from a parallel-load register (HW8 4.51)? | Connect register Q output through a 4-bit incrementer (adder with B=0001 Cin=0) back to register input I. Control logic: if clear=1 then load 0000 (ld=1 I=0000). Else if cnt=1 then load Q+1 (ld=1 I=Q+1). Else hold (ld=0). |
| What is a 4-bit up-counter with cnt clear and set built from a parallel-load register (HW8 4.52)? | Same as 4.51 but add set control. Priority: clear beats set beats cnt beats hold. If clear=1 load 0000. Else if set=1 load 1111. Else if cnt=1 load Q+1. Else hold. Use MUX to select which value to load. |
| What is the upper output for the 4-bit counter in problem 4.53 (HW8)? | upper=1 when counter value is 8 to 15. Since 8=1000 and 15=1111 the MSB Q3=1 for all values 8-15. So upper = Q3. Single wire connection from MSB of counter to upper output. |
| What is terminal count (tc) and how is it used (HW8 4.53 4.54)? | tc=1 when the counter reaches its maximum count value (1111 for 4-bit = 15). Equation: tc = Q3 AND Q2 AND Q1 AND Q0. Used to cascade counters: tc of lower counter connects to cnt of upper counter enabling it only when lower counter rolls over. |
| How do you design a 4-bit up-down counter with cnt_up cnt_down clear set (HW8 4.54)? | Use parallel-load register. Priority when multiple inputs=1: hold current value. Otherwise: if clear=1 load 0000. If set=1 load 1111. If cnt_up=1 load Q+1. If cnt_down=1 load Q-1. Use MUX to select correct load value. If two or more control inputs are 1 k |
| How do you design a circuit that outputs 1 every 99 clock cycles using up-counter (HW8 4.57a)? | Use a counter that counts 0 to 98. Detection logic: AND the bits that equal 98 (1100010): output = Q6 AND Q5 AND Q1. When output=1 also connect to synchronous clear so counter resets to 0 next clock edge. Output pulse lasts one clock cycle every 99 cycles |
| How do you design a circuit that outputs 1 every 99 clock cycles using down-counter (HW8 4.57b)? | Load counter with 98 (1100010). Count down each cycle. When count reaches 0 output done=1 (NOR of all Q bits). On next clock edge reload 98. Zero detection is simpler: just NOR all output bits. |
| What is the tradeoff between up-counter-clear vs down-counter-load for periodic pulse (HW8 4.57c)? | Up-counter: needs specific value detection logic (multiple AND/INV gates) but no parallel load hardware needed. Down-counter: needs parallel load hardware but zero detection is just a NOR gate (simpler). Down-counter detection is simpler; up-counter desig |
| How do you design a 14 MHz to 1 MHz clock divider using a down-counter (HW8 4.59)? | Need to divide by 14. Load counter with 13 (count 13 down to 0 = 14 cycles total). Counter width: 4 bits (2-to-the-4=16 > 14). When counter reaches 0 reload 13 and generate output pulse. Load value = 13 = 1101 binary. |
| How many clock cycles equal 5ms at 1 MHz for LED blink timer (HW9 4.60)? | 1 MHz clock period = 1 microsecond. 5ms = 5000 microseconds = 5000 clock cycles. Load timer with 5000 and count down to 0. |
| How many clock cycles equal 13ms at 1 MHz for LED blink timer (HW9 4.60)? | 13ms = 13000 microseconds = 13000 clock cycles at 1 MHz. Load timer with 13000 and count down to 0. |
| What is the FSM for the LED blink controller (HW9 4.60)? | Two states: ON (L=1, timer counts 5000 cycles) and OFF (L=0, timer counts 13000 cycles). Transitions: ON→OFF when timer done. OFF→ON when timer done. Controller loads appropriate timer value when entering each state. |
| How do you design a 300ms output pulse using a timer (HW9 E1a)? | At 1 MHz: 300ms = 300000 cycles. FSM: IDLE state (X=0, wait for B rising edge), ACTIVE state (X=1, load timer with 300000, count down). Transition ACTIVE→IDLE when timer reaches 0. Need at least 19-bit counter (2-to-the-19 = 524288 > 300000). |
| How do you design a 300ms output pulse using a register (HW9 E1b)? | Load a 19-bit register with 300000 when B rises. Decrement by 1 each clock cycle. Set X=1 while register value is nonzero (detect using NOR or comparator). When register reaches 0 stop decrementing and set X=0. Use a done flag or comparator output to sign |
| What is 27 times Q using strength reduction (HW9 4.47)? | 27 = 16 + 8 + 2 + 1. So 27Q = (Q<<4) + (Q<<3) + (Q<<1) + Q. Need three 12-bit adders and the shift operations are just wire connections. Compare: multiplier needs ~20 times n-squared transistors vs adders need ~20n transistors each. Massive savings. |
| What is Q divided by 3 approximation using shifts (HW9 4.48)? | 1/3 ≈ 0.333. Use: Q/3 ≈ (Q>>2) + (Q>>4) + (Q>>6) = 0.25 + 0.0625 + 0.015625 = 0.328. Accurate to hundredths place (0.33). Use wider internal wires before final truncation to prevent precision loss. |
| How do you trace a barrel shifter with x=1 y=0 z=1 and I=01100101 (HW9)? | Stage 1 x=1 shift left 4: 01010000. Stage 2 y=0 no shift: 01010000. Stage 3 z=1 shift left 1: 10100000. Q=10100000. Total shift = 4+0+1 = 5 positions left. |
| What x y z settings give a left shift of 6 in the barrel shifter (HW9)? | 6 = 4+2+0. x=1 (shift 4) y=1 (shift 2) z=0 (no shift). xyz=110. Each stage independently shifts by its power of 2 if control=1. |
| What is RTL design and what are its two components (HW10)? | RTL (Register Transfer Level) design describes behavior as data transfers between registers. Two components: 1. Datapath: registers and functional units (adders comparators shifters MUXes) that store and process data. 2. Controller: FSM that generates con |
| How does the controller interact with the datapath (HW10)? | Controller outputs → datapath control inputs: ld (load register), clr (clear register), sel (MUX select), cnt (count enable), add_en (enable adder). Datapath outputs → controller condition inputs: comparator results (lt eq gt tc done) used as FSM transiti |
| What is an HLSM (High-Level State Machine) (HW10 5.2 5.3)? | An FSM where state actions include data operations like register assignments (reg:=value) and arithmetic, and transition conditions can include comparisons of register values. Bridges behavioral description and RTL implementation. |
| What HLSM notation means load a register (HW10 5.7)? | reg := expression. Example: sum := A+B means on this clock edge load the sum register with the value A+B. The := symbol means register assignment happening on the clock edge when in this state. |
| How do you capture event counting as an HLSM (HW10 5.2)? | Need a register to store previous B value. HLSM: one state that loops. Action each cycle: if B XOR B_prev = 1 then C:=C+1. Always B_prev:=B. Output C continuously. Datapath needs: XOR gate, comparator or AND, 16-bit incrementer, 16-bit register C, 1-bit r |
| How do you capture up-down counter as HLSM (HW10 5.3)? | Detect rising edges of U and D using previous-value registers. States: IDLE (wait for button press). When U rises and not D: if C < 65535 then C:=C+1. When D rises and not U: if C > 0 then C:=C-1. When both: hold. Return to IDLE. |
| What datapath is needed for Figure 5.98 HLSM (HW10 5.7)? | Components: 16-bit adder (computes A+B or sum+C). MUX 2x1 on adder B-input (selects B or C). Register sum (16-bit). Register Sreg (16-bit). Comparator checking sum < 5099. Register or wire for P output. Controller drives: sum_ld, Sreg_ld, sel_B_or_C, P_va |
| What are the controller FSM states for Figure 5.98 HLSM (HW10 5.7)? | S0: reset state (Sreg:=0 sum:=0 P:=1). S1: wait for go (if go=0 stay). S2: sum:=A+B. S3: sum:=sum+C (loop back to S3 while sum<5099, exit when sum>=5099). S4: Sreg:=sum. Output S=Sreg P=P. |
| How do you derive the controller FSM from an HLSM (HW10 5.7 5.12)? | Each HLSM state becomes one or more controller states. Each data operation in an HLSM state becomes a controller state action (assert the correct control signals). HLSM transition conditions using data values become controller FSM transitions using compar |
| How do you design the RTL 4-bit up-counter using Figure 5.21 components (HW10 5.12)? | Datapath: register (reg) with clr and ld. Adder (add) with A=Q and B=0001 to compute Q+1. Comparator checking Q=1111 for tc output. Controller FSM: if clr=1 assert clr signal. Else if cnt=1 assert ld to load Q+1 into register. tc = comparator eq output wh |
| What is the averaging system design using RTL process (HW10 5.13)? | Datapath: two 8-bit registers (prev and curr). 9-bit adder (prev+curr). Right-shifter (divide by 2). Output truncated to 8 bits. Controller FSM: IDLE (wait for S rising edge). SAMPLE: prev:=curr, curr:=I. AVG: avg:=(prev+curr)>>1. Output avg continuously. |
| Why do you need 9-bit internal width for averaging two 8-bit numbers (HW10 5.13)? | Maximum sum = 255+255 = 510 = 111111110 in binary which needs 9 bits. Using 8-bit adder would overflow and lose the MSB giving wrong result. After shifting right by 1 the result fits in 8 bits again. |
| What is a parallel-load register and its control signals? | A register that loads all bits simultaneously. Control inputs: ld (load enable) - when 1 register captures input I on clock edge. clr (clear) - when 1 register resets to 0 on clock edge. When ld=0 and clr=0 register holds current value Q. |
| What is the priority of control signals on a register with clr and ld? | clr has higher priority than ld. If both clr=1 and ld=1 the register clears to 0. This is determined by the MUX/logic ordering in the register implementation. |
| What is a register with 2 control bits s1 s0 and four modes? | s1s0=00: Hold Q unchanged. s1s0=01: Load input I into Q. s1s0=10: Clear Q to 0. s1s0=11: Special operation (complement reverse nibble-swap etc depending on design). The two control bits select among four operations via internal MUXes. |
| How is a register with four modes implemented internally? | Each bit position has a 4-to-1 MUX. MUX inputs are: current Q (hold), input I (load), 0 (clear), special value (fourth operation). Select lines are s1 s0. MUX output feeds D input of the flip-flop. |
| What is an incrementer and how is it built? | A circuit that adds 1 to its n-bit input. Built as a ripple-carry adder with one input hardwired to 00...001. Or using half adders: LSB output = A0 XOR 1 = A0-complement, carry = A0. Each subsequent bit toggles only when all lower bits are 1. |
| What is a comparator and what are its outputs? | A magnitude comparator takes inputs A and B and produces: lt=1 when A<B, eq=1 when A=B, gt=1 when A>B. Exactly one output is 1 at all times. Used in controllers as condition signals for FSM transitions. |
| What is a 2-to-1 MUX and how is it used in datapaths? | Selects between two data inputs I0 and I1 based on select s0. When s0=0 output Q=I0. When s0=1 output Q=I1. Used in datapaths to route different data sources to the same functional unit or register input based on controller select signal. |
| What is a shifter component and its modes? | shiftL1: shift left 1 = multiply by 2. shiftL2: shift left 2 = multiply by 4. shiftR1: shift right 1 = divide by 2 (integer). The shift amount selects which mode. Shifting is implemented as wire connections with 0-fill, no actual gates needed for fixed sh |
| How do the five RTL datapath components connect together for a counter? | Register Q output connects to: adder input A (to compute Q+1) and comparator input A (to detect terminal count). Adder input B is hardwired to 0001. Adder output S connects to register input I. Comparator input B hardwired to 1111. Controller receives com |
| What is the complete signal flow in an RTL system? | External inputs → controller FSM (as condition inputs) and datapath (as data inputs). Controller state register → combinational next-state and output logic → control signals → datapath control inputs (ld clr sel cnt). Datapath status outputs (comparator r |
| What is the difference between a datapath status signal and a controller output signal? | Status signal: comes FROM datapath TO controller. Example: tc lt eq gt done. These are conditions the controller uses to decide state transitions. Control signal: goes FROM controller TO datapath. Example: ld clr sel cnt. These tell the datapath what oper |
| How do you find the FSM equivalent of an HLSM for the Figure 5.98 datapath (HW10 5.7)? | Replace each HLSM state action with controller signals: sum:=A+B becomes (assert sum_ld=1 sel=0 to pick B). sum:=sum+C becomes (assert sum_ld=1 sel=1 to pick C). Sreg:=sum becomes (assert Sreg_ld=1). Condition sum<5099 becomes comparator lt output signal |
| What is the two-sensor car speed system design (HW10 E2)? | Datapath: free-running counter (increments every clock cycle). Controller FSM: IDLE state (wait for sensor1=1). TIMING state (counter running, wait for sensor2=1). DONE state (read counter value = elapsed time t, output speed = distance/t using divider or |
| How many bits does the timer counter need for 300ms at 1MHz (HW9 E1)? | 300ms = 300000 cycles. 2-to-the-18 = 262144 (not enough). 2-to-the-19 = 524288 > 300000. Need 19-bit counter. Load value = 300000 = 1001001001111100000 in binary. |
| What are the design steps for a modulus-N counter from scratch? | 1. Determine number of flip-flops needed: ceil(log2(N)). 2. Draw state diagram with N states 0 through N-1. 3. Add synchronous clear when count = N (transition back to 0). 4. Derive next-state equations. 5. Implement detection logic for value N using AND/ |
| How does cascading two 4-bit counters create an 8-bit counter? | Lower counter: counts freely 0-15. Its tc output (Q3 AND Q2 AND Q1 AND Q0) goes HIGH for one cycle when it reaches 15. Connect lower tc to cnt input of upper counter. Upper counter only increments when lower overflows. Combined count range: 0 to 255. |
| What is the complete truth table structure for reverse engineering a 2-state-bit 1-input circuit (HW7 3.48)? | 8 rows total: s1 s0 a = 000 001 010 011 100 101 110 111. For each row compute n1 n0 y from the gate equations. Group by s1 s0 value to identify 4 states. Each state has 2 rows (a=0 and a=1) showing which state to go to next. |
| How do you verify FSM transition completeness after reverse engineering? | For each state OR all its outgoing transition conditions. Result must equal 1 (always true). If OR result is not always 1 there are missing transitions (incomplete). Also AND each pair of conditions - if any AND = 1 transitions are non-exclusive (ambiguou |
| What is the sequence generator controller truth table from Figure 3.68 (HW7 3.52)? |
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