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Digital Circuits
Stats and Prob
| Question | Answer |
|---|---|
| What is the divide-by-2 method for decimal to binary? | Repeatedly divide by 2, record remainders, read remainders bottom to top. Example: 9→1001 |
| Convert decimal 15 to binary | 15÷2=7R1, 7÷2=3R1, 3÷2=1R1, 1÷2=0R1 → 1111 |
| Convert decimal 32 to binary | 32÷2=16R0, 16÷2=8R0, 8÷2=4R0, 4÷2=2R0, 2÷2=1R0, 1÷2=0R1 → 100000 |
| Convert decimal 140 to binary | 140→70R0→35R0→17R1→8R1→4R0→2R0→1R0→0R1 → 10001100 |
| Convert decimal 9 to binary | 9÷2=4R1, 4÷2=2R0, 2÷2=1R0, 1÷2=0R1 → 1001 |
| How do you convert binary to decimal? | Multiply each bit by 2 raised to its position (from right starting at 0) then sum. Example: 1011 = 8+0+2+1 = 11 |
| Convert binary 100 to decimal | 1×4 + 0×2 + 0×1 = 4 |
| Convert binary 1011 to decimal | 1×8 + 0×4 + 1×2 + 1×1 = 11 |
| Convert binary 111111 to decimal | 32+16+8+4+2+1 = 63 |
| Convert binary 101010 to decimal | 32+0+8+0+2+0 = 42 |
| How do you convert binary to hexadecimal? | Group bits into groups of 4 from the right, convert each group to its hex digit. Example: 11001101 → 1100 1101 → CD |
| Convert binary 11001101 to hex | 1100 1101 → CD |
| Convert binary 10100101 to hex | 1010 0101 → A5 |
| Convert binary 11110001 to hex | 1111 0001 → F1 |
| Convert binary 1101101111100 to hex | Pad: 0001 1011 0111 1100 → 1B7C |
| How do you convert hex to binary? | Replace each hex digit with its 4-bit binary equivalent. Example: FF → 1111 1111 |
| Convert hex FF to binary | 1111 1111 |
| Convert hex F0A2 to binary | 1111 0000 1010 0010 |
| Convert hex 0F100 to binary | 0000 1111 0001 0000 0000 |
| Convert hex 3E2A to binary | 0011 1110 0010 1010 |
| Convert hex 101 to binary | 0001 0000 0001 |
| How do you convert hex to decimal? | Multiply each hex digit by 16 raised to its position from the right and sum. Example: FF = 15×16 + 15 = 255 |
| Convert hex FF to decimal | 15×16 + 15 = 255 |
| Convert hex F0A2 to decimal | 15×4096 + 0×256 + 10×16 + 2 = 61440+0+160+2 = 61602 |
| Convert hex 0F100 to decimal | 0×65536 + 15×4096 + 1×256 + 0+0 = 61440+256 = 61696 |
| Convert hex 100 to decimal | 1×256 + 0+0 = 256 |
| How do you convert binary to octal? | Group bits into groups of 3 from the right, convert each group to its octal digit (0-7) |
| How do you convert octal to binary? | Replace each octal digit with its 3-bit binary equivalent |
| What is ASCII encoding? | A standard mapping of characters to 7-bit binary codes. Example: A=1000001, space=0100000 |
| Encode L in ASCII (from Figure 1.9) | 100 1100 |
| Encode E in ASCII | 100 0101 |
| Encode T in ASCII | 101 0100 |
| Encode space in ASCII | 010 0000 |
| Encode ! in ASCII | 010 0001 |
| Encode S in ASCII | 101 0011 |
| Encode dollar sign in ASCII | 010 0100 |
| Encode digit 1 in ASCII | 011 0001 |
| Encode digit 2 in ASCII | 011 0010 |
| Encode digit 0 in ASCII | 011 0000 |
| What is BCD (Binary Coded Decimal)? | Each decimal digit is separately encoded as a 4-bit binary number. Example: 59 = 0101 1001. Codes 1010-1111 are invalid. |
| What is Gray code? | A numbering system where consecutive values differ by exactly 1 bit. Used to prevent errors in digital systems. |
| How do you convert binary to Gray code? | MSB stays the same. Each subsequent Gray bit = XOR of current and previous binary bits. Example: 1011 → 1110 |
| How do you convert Gray code to binary? | MSB stays the same. Each subsequent binary bit = XOR of previous binary bit and current Gray bit. |
| What is the voltage encoding if 0V=00, 1V=01, 2V=10, 3V=11 and input is 1111101010010000? | Pairs: 11=3V, 11=3V, 10=2V, 10=2V, 10=2V, 01=1V, 00=0V, 00=0V each held for 1ms |
| How large would a 50-million transistor phone be using vacuum tubes at 1 cubic inch each? | 50,000,000 cubic inches which is approximately 28,935 cubic feet — roughly the size of a large building |
| What is the Boolean equation for a flood detector: pump on if water detected AND system enabled? | P = W AND E |
| What is the Boolean equation for an alarm: night AND light detected AND no motion? | Alarm = N AND L AND M-complement |
| What is the Boolean equation for an irrigation valve: enabled AND no rain AND no freeze? | Valve = E AND R-complement AND Z-complement |
| Evaluate F = a AND (b OR c) AND d for a=1 b=1 c=0 d=1 | b OR c = 1, F = 1 AND 1 AND 1 = 1 |
| Evaluate F = a AND (b OR c) AND d for a=0 b=0 c=0 d=1 | F = 0 AND 0 AND 1 = 0 |
| Evaluate F = a AND (b OR c) AND d for a=1 b=0 c=0 d=0 | F = 1 AND 0 AND 0 = 0 |
| Evaluate F = a AND (b OR c) AND d for a=1 b=0 c=1 d=1 | b OR c = 1, F = 1 AND 1 AND 1 = 1 |
| For a NAND transistor circuit when A=1 and B=1 what is the output? | Both series NMOS transistors conduct (pull-down path active), both parallel PMOS are off. Output Y = 0 since NOT(1 AND 1) = 0 |
| For a NOR transistor circuit when A=1 and B=0 what is the output? | A=1 activates pull-down NMOS for A. A=1 turns off A PMOS so no pull-up path. Output Y = 0 since NOT(1 OR 0) = 0 |
| Evaluate F = ab-complement + bc-complement + c for a=1 b=0 c=1 | ab-comp = 1x1=1, bc-comp = 0x0=0, c=1. F=1 |
| Evaluate F = ab-complement + bc-complement + c for a=0 b=1 c=0 | ab-comp=0x0=0, bc-comp=1x1=1, c=0. F=1 |
| Evaluate F = ab + b-complement c d-complement for a=1 b=0 c=1 d=0 | ab=0, b-comp=1, d-comp=1, b-comp x c x d-comp=1. F=1 |
| Evaluate F = ab + b-complement c d-complement for a=0 b=1 c=0 d=1 | ab=0, b-comp=0. F=0 |
| Evaluate F = ab + b-complement c d-complement for a=0 b=0 c=1 d=1 | ab=0, b-comp=1, d-comp=0. F=0 |
| What is the truth table for F(a,b,c) = ab-complement c + ab? | 000=0, 001=0, 010=0, 011=0, 100=0, 101=1, 110=1, 111=1 |
| Are F=ab-complement and G=(a-complement + ab)-complement equivalent? | Yes. Simplify G: a-complement+ab = a-complement+b by absorption, then (a-complement+b)-complement = ab-complement = F |
| What are the basic Boolean identity laws? | A+0=A, A times 1=A, A+1=1, A times 0=0, A+A=A, A times A=A, A+A-complement=1, A times A-complement=0 |
| State DeMorgan's Theorems | (AB)-complement = A-complement + B-complement and (A+B)-complement = A-complement times B-complement. Break the bar and change the operator. |
| What is the absorption law in Boolean algebra? | A + AB = A and A(A+B) = A. Also A + A-complement B = A + B |
| What is a Karnaugh Map used for? | To minimize Boolean functions by visually grouping adjacent 1s. Groups must be powers of 2 in size. |
| What are the rules for K-map groupings? | Groups must be rectangles of size 1,2,4, or 8. Only group 1s. Groups can wrap edges. Use largest possible groups. Every 1 must be covered. |
| What does each K-map group size eliminate? | Group of 2 eliminates 1 variable, group of 4 eliminates 2 variables, group of 8 eliminates 3 variables |
| Minimize F(a,b,c) = a-complement bc + ab using a K-map | Minterms at 011,110,111. Group 110+111=ab. Group 011+111=bc. Minimized: F = ab + bc |
| Minimize F(a,b,c) = ab + ac + ab-complement c-complement + c-complement | Group 1s on K-map. Result: F = a + c-complement |
| What is SOP (Sum of Products)? | A Boolean expression written as an OR of AND terms (minterms). Example: F = ab-complement + bc + a-complement c |
| What is POS (Product of Sums)? | A Boolean expression written as an AND of OR terms (maxterms). Example: F = (a+b)(b-complement+c) |
| What is a minterm? | A product term where every variable appears exactly once. For n variables there are 2-to-the-n minterms labeled m0 to m(2n-1). |
| What is a maxterm? | A sum term where every variable appears exactly once. Maxterm Mi is the complement of minterm mi. |
| What is canonical SOP notation? | Writing F as a sum of all minterms where F=1. Written as F = sum-of-minterms(list of minterm numbers). |
| What is a MUX (multiplexer)? | A many-to-one selector. A 2n-by-1 MUX has 2n data inputs, n select lines, and 1 output. Select lines choose which input passes to output. |
| What is the Boolean equation for a 2-by-1 MUX? | F = S-complement times D0 + S times D1 |
| How do you build an 8-by-1 MUX from two 4-by-1 MUXes? | Connect top 4 inputs to MUX1 and bottom 4 to MUX2 using S1 S0 for both. Use S2 to select between MUX1 and MUX2 outputs via a final 2-by-1 MUX. |
| How do you build an 8-by-1 MUX using gates? | Use 3 select lines S2 S1 S0. Each data input Di is ANDed with the appropriate minterm of S2 S1 S0, then all 8 AND outputs are ORed together. |
| What is a decoder? | A circuit with n inputs and 2n outputs where exactly one output is HIGH for each input combination. |
| How do you build a 4-by-16 decoder from five 2-by-4 decoders? | Use top 2 input bits to drive one 2-by-4 decoder whose 4 outputs enable four 2-by-4 decoders. Bottom 2 bits feed all four lower decoders giving 16 total outputs. |
| What is an encoder? | The opposite of a decoder. Has 2n inputs and n outputs. Outputs the binary code of whichever input is active. |
| What is a priority encoder? | An encoder where if multiple inputs are active, the highest-priority (usually highest-index) input determines the output. Includes a valid output V. |
| How do you implement a function using a 16-by-1 MUX? | Set Di=1 for each minterm where F=1 and Di=0 otherwise. Use all input variables as select lines. |
| How do you implement F(a,b,c,d)=sum(1,3,4,11,12,13,14,15) using a 16-by-1 MUX? | Set D1=D3=D4=D11=D12=D13=D14=D15=1, all others=0. Use a,b,c,d as select lines S3 S2 S1 S0. |
| How do you implement a function using a decoder? | Connect decoder outputs for all minterms where F=1 to an OR gate. The OR output is F. |
| How do you implement F(a,b,c,d)=sum(1,3,4,11,12,13,14,15) using two 3-by-8 decoders? | Use one decoder for minterms 0-7 and one for 8-15 (enabled by MSB). OR together outputs at positions 1,3,4 from first and 3,4,5,6,7 from second. |
| What is a DEMUX (demultiplexer)? | A one-to-many circuit that routes a single input to one of 2n outputs based on n select lines. Functions like a decoder with a data enable input. |
| What is the collision detection circuit for 4 computers (C=1 when 2 or more send)? | C = M0M1 + M0M2 + M0M3 + M1M2 + M1M3 + M2M3 (minimized via K-map) |
| What are the prime numbers in the range 0-15 for the prime detector circuit? | 2(0010), 3(0011), 5(0101), 7(0111), 11(1011), 13(1101) |
| For the low fuel indicator with 3-bit level, when is L=1? | When fuel level is 000, 001, or 010 (below level 3 which is 011). Minimized: L = F2-complement AND (F1-complement OR F0-complement) |
| What is a 2-bit comparator that detects a less-than-or-equal-to b? | Let a=a1a0 and b=b1b0. a less-or-equal b = (a1-comp)(a0-comp) + (a1-comp)(b1) + (b1)(b0) + (a1-comp)(b0) + (a0-comp)(b1) ... minimize via K-map for exact result |
| What is the function of the 8-by-1 MUX circuit in problem 10 of HW2? | With inputs D0=x, D1=1, D2=0, D3=x-complement, D4=z-complement, D5=y, D6=0, D7=1 and select lines S2=y-complement S1=x S0=1, F is determined by evaluating the selected data input |
| What is the basic structure of a Verilog module? | module name(input a, input b, output f); assign f = a and b; endmodule |
| What is a Verilog testbench? | A simulation module with no ports that instantiates the design, applies stimuli using initial blocks, and monitors outputs using dollar-monitor or dollar-display. |
| What is the difference between assign and always in Verilog? | assign is for continuous combinational logic. always at-star is for combinational procedural logic. always at posedge clk is for sequential clocked logic. |
| How do you describe a 2-by-1 MUX in Verilog? | assign F = S ? D1 : D0; or use always block with if-else |
| How do you simulate a circuit with only NAND gates in Verilog? | Use only nand gate primitives or express all logic using NOT of AND. Example: nand(out, a, b); for each gate in the circuit. |
| Why are NAND and NOR called universal gates? | Any Boolean function can be implemented using only NAND gates or only NOR gates. |
| How do you implement NOT using a single NAND gate? | Connect both inputs of the NAND to the same signal A. Output = NOT(A AND A) = NOT A |
| How do you implement AND using NAND gates? | Use one NAND gate then invert its output with a second NAND used as NOT. Two NAND gates total. |
| How do you implement OR using NAND gates? | Invert both inputs with NANDs used as NOT, then NAND the results. By DeMorgan: NOT(NOT A AND NOT B) = A OR B. Three NAND gates total. |
| How do you implement OR using NOR gates? | Connect both inputs of a NOR to the same signal to make NOT, invert both inputs, then NOR them together. |
| What is a basic SR latch and its truth table? | S=0 R=0: Hold (no change). S=1 R=0: Set Q=1. S=0 R=1: Reset Q=0. S=1 R=1: Forbidden/invalid state. |
| In a basic SR latch what happens when S0 goes from 1 to 0 while R0 stays 1? | Q remains 0. No change because S=0 R=1 is the Reset condition and Q was already 0. |
| In a basic SR latch what happens when S0 goes from 0 back to 1 while R0 is 1? | S=1 R=1 is the forbidden state. Output is undefined/invalid. |
| What is a level-sensitive SR latch with control? | An SR latch with an extra control input C. When C=1 the latch responds to S and R. When C=0 the latch holds its current state regardless of S and R. |
| In a level-sensitive SR latch with control how are internal signals S1 and R1 computed? | S1 = C AND S. R1 = C AND R. These feed into the basic SR latch. |
| When C=0 in a level-sensitive SR latch with control what happens to Q? | Q holds its current value. Changes on S or R have no effect because S1 and R1 are both forced to 0. |
| When C=1 and S=1 R=0 in a level-sensitive SR latch with control what happens? | S1=1 R1=0 so the latch is Set and Q becomes 1. |
| When C=1 and S=0 R=1 in a level-sensitive SR latch with control what happens? | S1=0 R1=1 so the latch is Reset and Q becomes 0. |
| When C=1 and S=0 R=0 in a level-sensitive SR latch with control what happens? | S1=0 R1=0 so the latch holds its current Q value. |
| What is a D latch? | A level-sensitive storage element with inputs D and C. When C=1 Q follows D. When C=0 Q holds its last value. Eliminates the forbidden state of SR latch. |
| How does a D latch derive S and R from input D? | S = D and R = D-complement. This ensures S and R are never both 1. |
| In a D latch when C=1 and D changes from 0 to 1 what happens to Q? | Q follows D and becomes 1 after a small gate delay. |
| In a D latch when C goes from 1 to 0 what happens to Q? | Q holds the last value of D that was present when C fell to 0. |
| In a D latch if C=1 for a long time and D changes multiple times what happens? | Q tracks every change in D while C=1. This is called transparency and can cause trickle-through problems. |
| What is the trickle-through problem with D latches? | When multiple D latches are in series and C is high for a long time, data can propagate through more than one latch in the same clock cycle. |
| How do edge-triggered D flip-flops solve the trickle-through problem? | They only capture D at the clock edge (rising or falling) and ignore D at all other times, so data cannot trickle through multiple flip-flops in one cycle. |
| What is a master-servant (master-slave) D flip-flop? | Two D latches in series. Master latch is enabled when clock is low (Cm = CLK-complement). Servant latch is enabled when clock is high (Cs = CLK). Output Q updates only on the rising clock edge. |
| In a master-slave D flip-flop when does the master latch capture D? | When CLK=0 (clock low). The master is transparent and follows D while clock is low. |
| In a master-slave D flip-flop when does the servant latch update Q? | When CLK rises to 1. The servant captures what the master stored and presents it as Q. |
| What is the key difference between a D latch and a positive-edge D flip-flop? | D latch: Q follows D whenever C=1 (level-sensitive). D flip-flop: Q captures D only at the rising clock edge (edge-triggered). The flip-flop ignores D at all other times. |
| What is a positive edge-triggered D flip-flop behavior? | Q takes the value of D at the moment of the rising clock edge and holds it until the next rising edge. |
| What is a negative edge-triggered D flip-flop? | Q captures D at the falling clock edge (when clock goes from 1 to 0). |
| What is setup time for a flip-flop? | The minimum time D must be stable BEFORE the active clock edge for correct operation. |
| What is hold time for a flip-flop? | The minimum time D must remain stable AFTER the active clock edge for correct operation. |
| What happens if setup or hold time is violated in a flip-flop? | The flip-flop may enter a metastable state where Q is neither clearly 0 nor 1 for an unpredictable time. |
| How do you delay a signal by two clock cycles using D flip-flops? | Connect X to D of FF1. Connect Q of FF1 to D of FF2. Connect Q of FF2 to output Y. All flip-flops share the same clock. |
| What is a Verilog gate-level model of a rising-edge D flip-flop? | Use two D latches: master enabled by CLK-complement and servant enabled by CLK. Implement each latch using NAND or NOR gates. |
| What is the Verilog testbench scenario for the D flip-flop simulation in HW5? | S=0 for 4ns, S=1 for 4ns, D=0 for 45ns, D=1 for 40ns, D=0 for 40ns. Monitor shows time clk S R D Q Qb at each change. |
| What is the difference between a falling-edge and rising-edge D flip-flop in master-slave design? | Rising-edge: master enabled when CLK=0, servant when CLK=1, Q updates on rising edge. Falling-edge: master enabled when CLK=1, servant when CLK=0, Q updates on falling edge. |
| What is a carry-ripple adder? | A chain of full adders where the carry-out of each stage feeds into the carry-in of the next. Simple but slow because carries must ripple through all stages. |
| What is the propagation delay of an n-bit carry-ripple adder if each gate has delay 1ns? | Each full adder has 2 gate delays for carry. Total = 2n gate delays. For 8-bit: 2 times 8 = 16ns for carry plus 1 more for final sum = longest path is approximately 2n+1 gate delays. |
| What is the longest time to add two numbers with an 8-bit carry-ripple adder assuming 1ns per gate? | The critical path goes through the carry chain. Each full adder needs 2 gate delays for carry output. Total = 2 times 8 = 16ns plus 1ns for final sum = approximately 17ns. |
| How do you trace a 3-bit carry-ripple adder adding 111 and 011? | At time 0: all outputs 0. After delay 1: FA0 produces S0=0 C0=1. After delay 2: FA1 uses C0=1 produces S1=1 C1=1. After delay 3: FA2 uses C1=1 produces S2=1 C2=1. Final result: S=110 Cout=1 meaning decimal 10. |
| What is a 5-bit adder input and output range for unsigned numbers? | Inputs: each 5-bit number ranges from 0 to 31. Output: 6 bits (including carry-out) ranges from 0 to 62. |
| Show adding 10011 and 00111 step by step | 10011 (19) + 00111 (7). From LSB: 1+1=0C1, 1+1+1=1C1, 0+1+1=0C1, 0+0+1=1C0, 1+0+0=1C0. Result: 011010 = 26. Correct: 19+7=26. |
| What is a 4-bit incrementer? | A circuit that adds 1 to a 4-bit number. Implemented as a carry-ripple adder with B inputs all tied to 0 and Cin tied to 1. |
| How do you build a 10-bit carry-ripple adder from 4-bit carry-ripple adders? | Use three 4-bit adders. First handles bits 0-3. Second handles bits 4-7 with Cin from first adder Cout. Third handles bits 8-9 (2-bit) or a third 4-bit adder with Cin from second Cout. |
| How do you add three 8-bit signed numbers using 8-bit carry-ripple adders? | Use two 8-bit adders in sequence. First adder computes A+B. Then sign-extend the 9-bit result to 9 bits and add C using a second adder. Handle overflow carefully. |
| What is a pure encoder? | A circuit with 2n inputs and n outputs where exactly one input is active at a time. Outputs the binary code of the active input. Does not handle multiple active inputs. |
| What is an 8-to-3 pure encoder truth table? | One of inputs I0-I7 is 1. Output Y2Y1Y0 = binary index of active input. Example: I5=1 → Y2Y1Y0=101. |
| What is a priority encoder? | An encoder where if multiple inputs are active simultaneously, the highest-priority (highest-index) active input determines the output. Includes a valid output V=1 when any input is active. |
| What is the difference between a pure encoder and a priority encoder? | Pure encoder: only one input active at a time, undefined behavior if multiple active. Priority encoder: handles multiple active inputs by selecting the highest-priority one. |
| What are the Boolean equations for an 8-to-3 priority encoder outputs? | Y0 = I1 + I3 + I5 + I7. Y1 = I2 + I3 + I6 + I7. Y2 = I4 + I5 + I6 + I7. V = I0+I1+I2+I3+I4+I5+I6+I7. |
| What does a magnitude comparator output? | Three outputs: AgtB (A greater than B), AeqB (A equal to B), AltB (A less than B). Exactly one output is 1 for any given inputs. |
| What are the equations for a single-bit magnitude comparator stage? | out_gt = in_gt + (in_eq AND a AND b-complement). out_lt = in_lt + (in_eq AND a-complement AND b). out_eq = in_eq AND (a XNOR b). |
| How does a 4-bit ripple magnitude comparator work? | Compares bits from MSB to LSB. Each stage takes in_gt in_eq in_lt from the previous stage. Stage 3 (MSB) starts with in_gt=0 in_eq=1 in_lt=0. Final stage 0 outputs AgtB AeqB AltB. |
| Trace the 4-bit magnitude comparator for a=15 (1111) and b=12 (1100) | Stage3: a3=1 b3=1 equal → out_eq=1. Stage2: a2=1 b2=1 equal → out_eq=1. Stage1: a1=1 b1=0 a greater → out_gt=1. Stage0: out_gt propagates → AgtB=1 AeqB=0 AltB=0. |
| How do you design a system to check if three 4-bit numbers are equal? | Use two 4-bit magnitude comparators. Compare A and B with first comparator. Compare B and C with second comparator. AND the two AeqB outputs. Output is 1 only if A=B AND B=C. |
| How do you detect if an 8-bit input equals 99 using an equality comparator? | Connect the 8-bit input to the A port of an 8-bit comparator and connect 99 (01100011) hardwired to the B port. Output AeqB is 1 when input equals 99. |
| How do you detect if an 8-bit input equals 99 using gates only? | 99 = 01100011. Use inverters on bits that must be 0 (bits 7,4,3,0 wait — 99=01100011 so invert bits 7,4,3). AND all 8 lines together (inverted where bit=0). Result is 1 only for input 99. |
| How do you compute the minimum of three 8-bit numbers using magnitude comparators? | Compare A and B: if AltB select A else select B into temp. Compare temp and C: if temp less than C select temp else select C. Use 2-to-1 MUXes controlled by the comparator AltB output. |
| How do you compute the maximum of two 16-bit numbers using a magnitude comparator? | Compare A and B with a 16-bit comparator. Use AgtB output to control a 16-bit 2-to-1 MUX. If AgtB=1 output A else output B. |
| How do you design a circuit that outputs 1 when 8-bit input a is between 75 and 100 inclusive? | Use two 8-bit comparators. First checks a >= 75 (AgeB with B=75, use AgtB OR AeqB). Second checks a <= 100 (AleB with B=100). AND both outputs. Result is 1 when 75 <= a <= 100. |
| How do you model a 1-bit full adder in Verilog? | module full_adder(input a, b, ci, output s, co); assign s = a ^ b ^ ci; assign co = (a&b)|(b&ci)|(a&ci); endmodule |
| How do you model a 4-bit adder in Verilog using a 1-bit full adder? | Instantiate four full_adder modules. Connect carry-out of each to carry-in of the next. First carry-in tied to 0. Example: full_adder FA0(a[0],b[0],1b0,s[0],c1); |
| How do you represent signed numbers in Verilog for testing? | Use the signed keyword or represent in 2s complement. Example: -5 in 4 bits = 4b1011. -1 = 4b1111. The adder logic is the same for signed and unsigned. |
| What is 2s complement addition for signed: a=-5 b=-1 using 4-bit adder? | -5 = 1011, -1 = 1111. Sum = 1011+1111 = 11010. Lower 4 bits = 1010 = -6. Correct: -5+(-1)=-6. |
| What is 2s complement addition for signed: a=9 b=-2 using 4-bit adder? | 9=1001, -2=1110. Sum=1001+1110=10111. Lower 4 bits=0111=7. Correct: 9+(-2)=7. |
| What is the formula for clock period given frequency? | Period T = 1 divided by frequency f. Example: 100 MHz → T = 1/100,000,000 = 10 ns |
| Compute clock period for 32.768 kHz | T = 1/32768 ≈ 30.52 microseconds |
| Compute clock period for 100 MHz | T = 1/100,000,000 = 10 ns |
| Compute clock period for 1.5 GHz | T = 1/1,500,000,000 ≈ 0.667 ns |
| Compute clock period for 2.4 GHz | T = 1/2,400,000,000 ≈ 0.417 ns |
| Compute clock frequency for period 1 second | f = 1/1 = 1 Hz |
| Compute clock frequency for period 1 ms | f = 1/0.001 = 1 kHz |
| Compute clock frequency for period 20 ns | f = 1/20ns = 50 MHz |
| Compute clock frequency for period 1 ns | f = 1/1ns = 1 GHz |
| Compute clock frequency for period 20 ps | f = 1/20ps = 50 GHz |
| Compute clock frequency for period 400 ns | f = 1/400ns = 2.5 MHz |
| What is a parallel-load register? | A register that loads all bits simultaneously on a clock edge when the load control input ld=1. When ld=0 the register holds its current value. |
| How does an 8-bit parallel-load register behave when ld=0? | Q holds its current value at every rising clock edge regardless of what is on input I. |
| How does an 8-bit parallel-load register behave when ld=1? | Q captures the value of input I at the next rising clock edge. |
| What is a synchronous clear input (clr) on a register? | When clr=1 the register resets to all zeros on the next rising clock edge. It is synchronous because the clear only takes effect at the clock edge not immediately. |
| What is the priority between clr and ld when both are 1 on a register? | Clear (clr) typically has priority over load (ld). When clr=1 the register clears to 0 regardless of ld. |
| What are the four modes of the 4-bit register in problem 4.3? | S1S0=00: Hold current value. S1S0=01: Load inputs I3-I0. S1S0=10: Clear to 0000. S1S0=11: Complement all bits (0000 becomes 1111). |
| What does complement mode do in a register? | Every bit is inverted. 0 becomes 1 and 1 becomes 0. Example: 1010 becomes 0101. |
| What does reverse-bits mode do in a register (problem 4.4)? | The bit order is reversed. MSB becomes LSB and vice versa. Example: 1110 becomes 0111. |
| What does nibble-swap mode do in an 8-bit register (problem 4.5)? | The high 4 bits and low 4 bits are exchanged. Example: 11110000 becomes 00001111. A nibble is 4 bits. |
| How do you design a radar gun speed-save register (problem 4.6)? | Use an 8-bit parallel-load register. Connect speed input S to register input I. Connect save button B to load control ld. Output Q feeds display D. Speed is only saved when B=1 at clock edge. |
| How do you design a system where R has priority over load inputs La Lb Lc (problem 4.7)? | Check R first: if R=1 perform the swap A=B B=C C=A using MUXes regardless of La Lb Lc. If R=0 load each register only if its corresponding L input is 1. |
| How do you store the last four values of an 8-bit input using registers and a MUX (problem 3.19)? | Chain four 8-bit registers. Each clock cycle the new input loads into Reg1 and each register shifts its value to the next. Use an 8-bit 4x1 MUX with s1 s0 to select which register output to display. |
| In problem 3.20 with three cascaded 4-bit registers what value does register b hold after the first clock edge? | Register b captures the output of register a. Since register a loads input a3..a0 on each clock edge, b gets the previous value of a after one clock cycle. |
| In a chain of three registers a-b-c what is the delay between input and register c output? | Register c output reflects the input value from 3 clock cycles ago since data passes through a then b then c one cycle at a time. |
| What is a Finite State Machine (FSM)? | A sequential circuit with a finite number of states, transitions between states based on inputs, and outputs. Has an initial state and uses flip-flops to store current state. |
| What is the difference between a Moore FSM and a Mealy FSM? | Moore: outputs depend only on current state. Mealy: outputs depend on current state AND current inputs. Mealy typically needs fewer states. |
| What are the steps to design an FSM? | 1. Understand problem and identify outputs needed. 2. Draw state diagram with states and transitions. 3. Create state transition table. 4. Assign binary codes to states. 5. Derive next-state and output equations. 6. Implement with flip-flops and gates. |
| What is a state transition diagram? | A graph where circles represent states and arrows represent transitions labeled with input conditions. Moore outputs are written inside the circle. Mealy outputs are written on the transition arrows. |
| Design an FSM where X=1 after A has been 1 for at least 3 cycles total (problem Q1) | Use a counter-style FSM. States track count of total 1s seen: S0(count=0) S1(count=1) S2(count=2) S3(count=3+). X=1 only in S3. Transition to next count state when A=1 stay in same state when A=0. |
| Design an FSM where Y=1 when A has been 1 for at least 2 consecutive cycles (problem Q1) | States: S0(no consecutive 1s) S1(one consecutive 1) S2(two or more consecutive 1s). Y=1 in S2. When A=1 advance state. When A=0 return to S0. |
| How many states does an FSM need to recognize the sequence 1101? | Minimum 5 states: initial and one state for each prefix matched: seen-1, seen-11, seen-110, seen-1101(accept). |
| How do you design an FSM that recognizes 1101 or 1110? | Draw states for shared prefixes: initial, seen-1, seen-11, seen-110, seen-111, accept-1101, accept-1110. Overlap common prefix states to minimize total states. |
| Draw the FSM for: Y=1 for two clock cycles whenever X changes from 0 to 1 (problem 3.24) | States: IDLE(Y=0 waiting for X rising edge), OUT1(Y=1 first cycle after X went to 1), OUT2(Y=1 second cycle), then return to IDLE. Transition IDLE to OUT1 when X=1 and previously 0. |
| Design an FSM with no inputs that sequences xyz: 000 001 010 100 repeat (problem 3.25) | Four states: S0(xyz=000) S1(xyz=001) S2(xyz=010) S3(xyz=100). Each rising clock edge advances to next state. After S3 return to S0. This is a Moore FSM. |
| How many flip-flops are needed to encode 4 states in an FSM? | 2 flip-flops since 2 bits can represent 4 states (00 01 10 11). |
| How does adding input I that pauses the sequence differ from I that resets it (problems 3.26 vs 3.27)? | 3.26 pause: when I=0 stay in current state. When I returns to 1 continue from current state. 3.27 reset: when I=0 stay in current state. When I returns to 1 go back to S0(000) and restart. |
| Design the wristwatch FSM with button B sequencing displays (problem 3.28) | Four states: TIME(s1s0=00) ALARM(s1s0=01) STOPWATCH(s1s0=10) DATE(s1s0=11). When B=1 transition to next state AND wait in a pressed state until B=0 before accepting another press. |
| Why must the wristwatch FSM wait for button B to be released? | To prevent advancing multiple states from one button press. The FSM must detect the rising edge of B not the level so it waits for B=0 before it can sequence again. |
| How do you add reset input R to the wristwatch FSM (problem 3.29)? | From any state if R=1 unconditionally transition to the TIME state (s1s0=00). R has priority over B. |
| What is a Gray code sequence? | A sequence where exactly one bit changes between consecutive values. Example for 3-bit: 000 010 011 001 101 111 110 100. |
| Design the Gray code FSM with gcnt input (problem 3.30) | Eight states for each Gray code value. When gcnt=1 advance to next state on rising clock edge. When gcnt=0 hold current state. Outputs x y z equal the current state encoding. |
| What is the next-state logic for the xyz=000 001 010 100 sequence FSM? | With 2-bit state encoding S1S0: 00→01→10→11→00. Next state equations: N1 = S1 XOR S0. N0 = S1-complement AND S0-complement OR S0... derive from transition table using K-map. |
| What is the output logic for a Moore FSM sequencing 000 001 010 100? | Outputs are directly the state encoding with one extra bit. State 00: xyz=000. State 01: xyz=001. State 10: xyz=010. State 11: xyz=100. Assign output bits from state bits. |
| How do you implement a 4-bit register with complement mode using D flip-flops? | For each bit i: Di = (S1-complement AND S0-complement AND Qi) OR (S1-complement AND S0 AND Ii) OR (S1 AND S0-complement AND 0) OR (S1 AND S0 AND Qi-complement). Use MUX logic. |
| How do you implement nibble-swap in an 8-bit register using MUXes? | When S1S0=11 connect Q7-Q4 to inputs I3-I0 and Q3-Q0 to inputs I7-I4. Use a MUX per bit to select between normal input and swapped input based on the S1S0=11 condition. |
| What is the load enable equation for register A in problem 4.7? | Load_A = (R-complement AND La) OR R. When R=1 load A with current value of B. When R=0 load A with input I only if La=1. |
| How do you trace a parallel-load register timing diagram when ld toggles? | At each rising clock edge: if ld=1 Q becomes current I value. If ld=0 Q holds previous value. clr=1 overrides and Q becomes 0 at clock edge. |
| What are the steps to convert an FSM to a controller? | Start with the FSM state diagram. 2Encode states with binary codes. 3Create a statetruth table (current state + inputs next state + outputs). 4Derive next-state logic equations. 5Derive outputequations. 6Implement with a state register ff n combina gate |
| What is a controller in digital design? | A circuit that implements an FSM using a state register (flip-flops storing current state) plus combinational logic that computes next-state and outputs from current state and inputs. |
| What two parts make up a controller implementation? | 1. State register: flip-flops that store the current state, updated on each clock edge. 2. Combinational logic: gates that compute the next state and outputs from current state bits and inputs. |
| How many flip-flops do you need for a controller with N states? | You need ceiling of log base 2 of N flip-flops. Example: 4 states need 2 flip-flops, 5-8 states need 3 flip-flops, 9-16 states need 4 flip-flops. |
| What is the state transition truth table in controller design? | A table listing every combination of current state bits and input bits as inputs, with next state bits and output bits as outputs. Used to derive logic equations. |
| How do you derive next-state equations from the state transition truth table? | Treat each next-state bit as a separate Boolean function of current state bits and inputs. Use K-maps or Boolean algebra to minimize each equation. |
| How do you convert the 4-state FSM of Figure 3.109 to a controller (states A B C D, input a, output y)? | Encode: A=00 B=01 C=10 D=11. Build truth table with s1 s0 a as inputs and n1 n0 y as outputs. Derive: y=s1. From each state: A→B if a-comp, A→A if a. B→C if a, B→B if a-comp. C→D if a, C→B if a-comp. D→A always. Minimize n1 n0 y with K-maps. |
| In Figure 3.109 FSM what is the output y for each state? | States A and D: y=0. States B and C: y=1. |
| How do you convert the Figure 3.110 FSM to a controller (inputs a b, output y)? | Encode states A=00 B=01 C=10 D=11. Build truth table with s1 s0 a b as 4 inputs giving 16 rows. Fill next state from diagram transitions. Derive minimized equations for n1 n0 and y using K-maps. |
| What is the controller design for the FSM where Y=1 for two cycles after X rises (exercise 3.41)? | Three states: S0(Y=0 waiting) S1(Y=1 cycle1) S2(Y=1 cycle2). Encode S0=00 S1=01 S2=10. Transitions: S0→S1 when X=1 and prev=0, else stay. S1→S2 always. S2→S0 always. y=s1 (either state 01 or 10 meaning y = n0 XOR n1 or directly from state bits). |
| What is the controller for the Gray code FSM exercise 3.43 with input gcnt? | 8 states need 3 flip-flops. States G0-G7 correspond to xyz outputs 000 010 011 001 101 111 110 100. When gcnt=1 advance to next state. When gcnt=0 hold current state. Next-state equations: if gcnt=0 then n2n1n0=s2s1s0 else next Gray code state. |
| What is a non-exclusive transition problem in an FSM? | When a state has two or more transitions whose conditions can be simultaneously true. To check: AND the transition conditions together. If result can be 1 the transitions are non-exclusive (ambiguous). |
| What is an incomplete transition problem in an FSM? | When a state does not have transitions covering all possible input combinations. To check: OR all transition conditions from that state. If result is not always 1 then some input combinations have no defined next state. |
| How do you prove transitions are exclusive? | AND all pairs of transition conditions from the same state. If every AND result simplifies to 0 the transitions are mutually exclusive and correct. |
| How do you prove transitions are complete? | OR all transition conditions from the same state. If the result simplifies to 1 (always true) the transitions are complete and cover all input cases. |
| What is glitching in a controller output? | Temporary incorrect output values that appear briefly after a clock edge while the combinational logic is still settling to its new values. Caused by different signal paths having different propagation delays. |
| How do registered outputs eliminate glitching? | By adding flip-flops at the controller outputs. The outputs only change on clock edges after the combinational logic has fully settled, eliminating temporary incorrect values. The tradeoff is outputs are delayed by one clock cycle. |
| What is the output equation for the sequence generator controller (Figure 3.68)? | w=s1, x=s1 AND s0-complement, y=s1-complement AND s0, z=s1-complement, n1=s1 XOR s0, n0=s0-complement. |
| What is the critical path delay for Figure 3.68 controller outputs with AND=2ns and inverter=1ns? | z = s1-complement: 1ns. x = s1 AND s0-complement: 1+2=3ns. y = s1-complement AND s0: 1+2=3ns. n1 = s1 XOR s0: 2ns. n0 = s0-complement: 1ns. Longest path is 3ns. |
| How do you design a controller with synchronous reset to state 1010 (problem 3.50)? | Use a 4-bit state register. When reset=1 on the clock edge load 1010 into the state register regardless of normal next-state logic. Use a MUX: if reset=1 select 1010, else select computed next state. |
| How do you reverse engineer a sequential circuit to find its FSM? | 1Identify state register bits. 2Write Boolean equations for each next-state bit from the combinational logic. 3Write output equations. 4Build state table by evaluating equations for all state and input combinations 5Draw state diagram from table. |
| What is a 4-bit up-counter? | A sequential circuit that increments its 4-bit output by 1 on each rising clock edge when cnt=1. Counts from 0 to 15 then rolls over to 0. Has 16 states total. |
| What is the count range of an n-bit up-counter? | 0 to 2-to-the-n minus 1. Example: 4-bit counts 0-15, 8-bit counts 0-255, 16-bit counts 0-65535, 32-bit counts 0 to 4,294,967,295. |
| How do you design a 4-bit up-counter using a parallel-load register? | Connect the register output Q through a 4-bit incrementer (adder with B=0001) back to the data input I. When cnt=1 set ld=1 to load Q+1. When cnt=0 set ld=0 to hold. When clear=1 load 0000. |
| How do you design a 4-bit up-counter using flip-flops and MUXes? | Each bit has a MUX selecting between hold and count-up behavior. For bit i: Di = Qi XOR (cnt AND Q0 AND Q1 AND...AND Q(i-1)). This is the ripple carry toggle logic. |
| What is a synchronous clear in a counter? | The counter resets to 0 on the next rising clock edge when clear=1. The reset does not happen immediately but waits for the clock edge. Contrast with asynchronous clear which resets immediately. |
| What is a synchronous set in a counter? | The counter loads all 1s (1111 for 4-bit) on the next rising clock edge when set=1. Synchronous means it waits for the clock edge. |
| What is the priority order when multiple counter control inputs are active simultaneously (problem 4.54)? | When two or more of cnt_up cnt_down clear set are simultaneously 1 the counter retains its current value. No operation is performed. |
| What is the upper output in problem 4.53? | upper=1 when the 4-bit counter value is between 8 and 15 inclusive. This is simply the MSB (Q3) of the counter since Q3=1 for values 8-15. |
| How long before a 64-bit counter rolls over if incremented 15000 times per day? | 2-to-the-64 divided by 15000 = 18,446,744,073,709,551,616 divided by 15000 ≈ 1.23 times 10-to-the-15 days ≈ 3.36 trillion years. Effectively never in practice. |
| Give the count range and rollover time at 1 Hz for common counter sizes | 8-bit: 0-255, 256 seconds. 16-bit: 0-65535, about 18 hours. 32-bit: 0 to ~4.3 billion, about 136 years. 64-bit: 0 to ~1.8×10-to-the-19, about 585 billion years. |
| How do you design a circuit that outputs 1 every 99 clock cycles using an up-counter with synchronous clear? | Use a counter that counts 0 to 98. When count reaches 98 output 1 and synchronously clear to 0 on the next clock edge. Detection logic: AND all bits corresponding to value 98 (1100010). |
| How do you design a circuit that outputs 1 every 99 clock cycles using a down-counter with parallel load? | Load the counter with 98. Count down to 0. When counter reaches 0 output 1 and reload 98 on next clock edge. Detection logic: NOR all output bits (all zeros = 0). |
| What are the tradeoffs between up-counter-with-clear vs down-counter-with-load for periodic pulse generation? | Up-counter: simpler detection logic for reaching max value but needs decode of specific count. Down-counter: simpler zero detection (just NOR all bits) but requires parallel load hardware. Down-counter zero detection is generally simpler. |
| How do you create a clock divider from 14 MHz to 1 MHz using a down-counter? | Divide 14 by 1 = 14. Load the down-counter with 13 (count 13 down to 0 = 14 cycles). Counter needs 4 bits (ceil log2 of 14 = 4). When counter reaches 0 reload 13 and toggle or pulse the output. |
| What is the width of the down-counter needed to divide 14 MHz to 1 MHz? | Need to count 14 clock cycles so load value is 13. 4-bit counter (can count 0-15) is sufficient. Load value = 13 = 1101 in binary. |
| What is an up-down counter? | A counter that can count up or count down depending on control inputs. cnt_up=1 increments. cnt_down=1 decrements. Typically with clear and set controls as well. |
| How many states does an FSM need for Y=1 for five cycles after X rises (problem 3.45)? | 7 states: S0(waiting Y=0), S1 through S5(Y=1 for 5 cycles), then back to S0. Need 3 flip-flops since ceil(log2(7))=3. |
| What is the controller truth table size for an FSM with 5 inputs and 3 state bits? | 2-to-the-(3+5) = 256 rows in the truth table. In general: 2-to-the-(state bits + input bits) rows. |
| What is the Gray code FSM controller for exercise 3.43 next-state when gcnt=0? | n2=s2, n1=s1, n0=s0. Hold current state. All next-state bits equal current state bits. |
| What is the Gray code FSM controller next-state when gcnt=1 in state 000? | Next state is 010 (second Gray code value). So n2=0, n1=1, n0=0. |
| What is the Gray code sequence for the 8-state FSM in exercise 3.30 and 3.43? | 000 → 010 → 011 → 001 → 101 → 111 → 110 → 100 → back to 000. Exactly one bit changes at each step. |
| What is a timer in digital design? | A counter connected to a clock that measures elapsed time. At a known clock frequency, loading a specific count value and counting down (or up) to a threshold achieves a precise time delay. Time = count divided by clock frequency. |
| How do you design an LED blink controller using a 32-bit microsecond timer at 1 MHz? | FSM has two states: LED_ON and LED_OFF. In LED_ON: set L=1, start timer, transition to LED_OFF when timer reaches 5000 (5ms). In LED_OFF: set L=0, start timer, transition to LED_ON when timer reaches 13000 (13ms). |
| How many clock cycles equal 5 ms at 1 MHz? | 1 MHz = 1,000,000 cycles per second. 5 ms = 0.005 seconds. 0.005 times 1,000,000 = 5000 clock cycles. |
| How many clock cycles equal 300 ms at 1 MHz? | 300 ms = 0.3 seconds. 0.3 times 1,000,000 = 300,000 clock cycles. |
| How do you design a 300ms pulse output using a timer (problem E1a)? | FSM: IDLE state (X=0, wait for B=1), ACTIVE state (X=1, load timer with 300000, count down). When timer reaches 0 return to IDLE. At 1 MHz each count = 1 microsecond so 300000 counts = 300ms. |
| How do you design a 300ms pulse output using a register (problem E1b)? | Use a 19-bit register (2-to-the-19 = 524288 > 300000). Load 300000 when B pressed. Decrement each clock cycle. Set X=1 while register is nonzero. When register reaches 0 set X=0. |
| What is an array-style multiplier? | An 8-bit array multiplier uses 8 rows of AND gates to form partial products (each row is multiplicand AND one bit of multiplier) then adds them with a series of adders. For n-bit inputs it has n rows and produces a 2n-bit result. |
| How does an 8-bit array multiplier work? | Row i: AND each bit of A with bit i of B, shifted left by i positions. These 8 partial products are then summed using 7 adders. Final result is 16 bits. |
| How do you compute F = A times B times C + 3 times D + 12 in hardware? | Step 1: Multiply A times B using a 16-bit multiplier → result M1. Step 2: Multiply M1 times C → result M2. Step 3: Multiply D by 3 (D shifted left 1 plus D) → result M3. Step 4: Add M2 + M3 + 12 using two 16-bit adders. |
| What is strength reduction in hardware design? | Replacing expensive operations like multiplications with cheaper ones like shifts and adds. Example: multiply by 4 becomes shift left 2. Reduces transistor count and propagation delay. |
| How do you compute 27 times Q using only shifts and adds? | 27 = 16 + 8 + 2 + 1. So 27Q = (Q shifted left 4) + (Q shifted left 3) + (Q shifted left 1) + Q. Three adders and three shifters replace one multiplier. |
| How do you approximate Q divided by 3 using shifts and adds? | 1/3 ≈ 0.33 ≈ 1/4 + 1/16 + 1/64 = 0.328. So Q/3 ≈ (Q shifted right 2) + (Q shifted right 4) + (Q shifted right 6). Use wider internal wires to prevent overflow before final truncation. |
| What is a barrel shifter? | A combinational circuit that can shift an input by any number of positions in a single operation. Implemented as stages of MUXes where each stage shifts by a power of 2 based on a control bit. |
| How does a 3-stage barrel shifter work with control bits x y z? | Stage 1 (controlled by x): shift left by 4 if x=1 else no shift. Stage 2 (controlled by y): shift left by 2 if y=1 else no shift. Stage 3 (controlled by z): shift left by 1 if z=1 else no shift. Total shift = 4x + 2y + z positions. |
| Trace the barrel shifter for I=01100101 x=1 y=0 z=1 | Stage 1 (x=1 shift left 4): 01010000. Stage 2 (y=0 no shift): 01010000. Stage 3 (z=1 shift left 1): 10100000. Final Q = 10100000. |
| What settings of x y z shift input left by 6 positions in the barrel shifter? | 6 = 4 + 2 + 0. So x=1 (shift 4), y=1 (shift 2), z=0 (no shift). xyz = 110. |
| What settings of x y z shift input left by 5 positions? | 5 = 4 + 0 + 1. So x=1 y=0 z=1. xyz = 101. |
| What settings of x y z shift input left by 3 positions? | 3 = 0 + 2 + 1. So x=0 y=1 z=1. xyz = 011. |
| How do you compute the average of four 8-bit inputs ignoring overflow? | Add all four 8-bit inputs using three adders then shift right by 2 (divide by 4). Ignoring overflow means using only 8-bit result even if sum exceeds 255. |
| How do you compute the average of four 8-bit inputs without losing information? | Use 10-bit internal wires (8 bits + 2 bits for overflow from adding 4 values max 255+255+255+255=1020 which needs 10 bits). Add with 10-bit adders then shift right 2 to get 8-bit average. |
| What is a special multiplier using shifts for multiply by 2 4 8 16 32 (problem 4.46)? | |
| What is RTL (Register Transfer Level) design? | A design abstraction where behavior is described as data transfers between registers controlled by a state machine. Consists of a datapath (registers adders comparators MUXes) and a controller (FSM). |
| What are the two main components of an RTL design? | 1. Datapath: contains registers and functional units (adders comparators shifters MUXes) that process and store data. 2. Controller: an FSM that generates control signals to direct the datapath operations. |
| What is an HLSM (High-Level State Machine)? | A state machine that includes data operations (like register assignments and arithmetic) directly in the state actions and transition conditions. It describes RTL behavior at a higher abstraction than a pure FSM. |
| How do you design an HLSM for counting edges on input B (problem 5.2)? | Single state with self-loop. On each clock edge: if B changed (detected by comparing current B with previous B stored in a register) then C = C + 1. Output C continuously. Use a register to store previous B value. |
| How do you detect an edge (0-to-1 or 1-to-0 transition) on a signal B? | Store the previous value of B in a flip-flop (B_prev). An edge occurred when B_prev XOR B = 1. A rising edge specifically is B_prev=0 AND B=1. |
| How do you design the HLSM for up-down counter with U and D buttons (problem 5.3)? | States detect button press (rising edge of U or D). When U rises and D=0: C = C+1 if C < max. When D rises and U=0: C = C-1 if C > 0. When both rise simultaneously: hold C. No rollover. |
| What datapath components are needed for the HLSM in Figure 5.98? | A 16-bit adder (to compute A+B and sum+C). A 16-bit comparator (to check sum less than 5099). Registers for sum and Sreg. A MUX to select between A+B and sum+C as adder input. Controller drives ld signals for each register. |
| What is the RTL design process? | 1. Capture behavior as HLSM. 2. Create datapath with registers and functional units for all operations in HLSM. 3. Connect datapath components. 4. Derive controller FSM from HLSM states and conditions. 5. Implement controller as state register plus combin |
| How do you create a datapath for the Figure 5.98 HLSM? | Registers: sum (16-bit) and Sreg (16-bit). Adder: 16-bit to compute A+B or sum+C (use MUX on adder input B to select between B and C). Comparator: checks sum < 5099. Controller signals: sum_ld (load sum register) Sreg_ld (load Sreg) sel (MUX select) P_ld |
| How do you use the RTL design process to build a 4-bit up-counter (problem 5.12)? | Datapath: 4-bit register with clear and load. 4-bit adder with one input tied to 0001 (incrementer). Comparator checking Q=15 for terminal count tc. Controller FSM: if clr=1 clear register. If cnt=1 load Q+1. Output tc=1 when Q=1111. |
| What is a terminal count (tc) output on a counter? | tc=1 when the counter reaches its maximum value (1111 for 4-bit = 15). Used to cascade counters or signal that a count period has completed. tc = Q3 AND Q2 AND Q1 AND Q0. |
| How do you cascade two 4-bit counters to make an 8-bit counter? | Connect tc (terminal count) of the lower 4-bit counter to the cnt (count enable) input of the upper 4-bit counter. Lower counter counts freely. Upper counter only increments when lower counter rolls over (tc=1). |
| How do you design a modulus-N counter? | Method 1 (up-counter with clear): count up and synchronously clear to 0 when count reaches N-1. Method 2 (down-counter with load): load N-1 and count down to 0 then reload N-1. Output pulse when count=0 or count=N-1. |
| What is a modulus-6 counter and how many states does it have? | A counter that counts 0 1 2 3 4 5 then repeats. It has 6 states (modulus = number of states). Needs 3 flip-flops. Clear when count reaches 6 (110) to return to 0. |
| How do you design a modulus-10 BCD counter? | Use a 4-bit counter. When count reaches 10 (1010) synchronously clear to 0. Detect 1010 using AND gate: clear = Q3 AND Q1 (since 1010 has Q3=1 Q1=1). Only 10 states: 0 through 9. |
| How does synchronous clear differ from asynchronous clear in a counter? | Synchronous clear: counter resets to 0 on the NEXT rising clock edge when clear=1. Asynchronous clear: counter resets to 0 IMMEDIATELY when clear=1 regardless of clock. Synchronous is preferred in clocked designs to avoid timing hazards. |
| How does parallel load work in a counter? | When load=1 the counter loads a preset value on the next rising clock edge instead of incrementing or decrementing. Used to set initial count value or reload value in down-counters for timers. |
| How do you design a down-counter timer for exactly T clock cycles? | Load the value T-1 on start. Count down to 0. When count reaches 0 output done=1 and reload T-1 for next cycle. The counter counts T states: T-1 T-2 ... 1 0. |
| How do you design a frequency divider that outputs 1 pulse for every N input clocks? | Use a modulus-N counter. The output pulses once every N clock cycles. Alternatively use a down-counter loaded with N-1 that outputs a pulse when it reaches 0 then reloads. |
| What is the relationship between shift left by N and multiplication? | Shifting a binary number left by N positions is equivalent to multiplying by 2-to-the-N. Example: shift left 3 = multiply by 8. This is the basis of strength reduction. |
| What is the relationship between shift right by N and division? | Shifting an unsigned binary number right by N positions is equivalent to integer division by 2-to-the-N. Example: shift right 2 = divide by 4 (truncated). For signed numbers arithmetic shift right preserves the sign bit. |
| How many transistors does a multiplier use versus a shift-and-add approach? | A full n-bit multiplier uses approximately n-squared AND gates plus n adders totaling roughly 20n-squared transistors. A shift-and-add for a constant multiplier uses only adders and wires totaling roughly 20n transistors per add. Much more efficient. |
| What is the datapath component library from Figure 5.21? | Register (reg): clr and ld inputs, parallel load, synchronous clear. Adder (add): S=A+B. Comparator (cmp): outputs lt eq gt for unsigned A vs B. Shifter (shift L/R): shifts left or right by 1 or 2. MUX 2x1: selects I0 or I1 based on s0. |
| How do you design the averaging system in problem 5.13? | Datapath: two 8-bit registers (prev and curr) to store last two samples. 9-bit adder to sum them without overflow (8+8=9 bits needed). Right shift by 1 to divide by 2. Output 8 bits. Controller: on rising edge of S shift curr to prev and load new I into c |
| What internal bit width is needed to average two 8-bit numbers without overflow? | 9 bits. Maximum sum of two 8-bit numbers is 255+255=510 which requires 9 bits. After dividing by 2 (shift right 1) the result fits in 8 bits again. |
| How does the two-sensor car speed measurement system work (problem E2)? | Sensor 1 triggers start: controller starts a timer counter. Sensor 2 triggers stop: controller reads timer value (elapsed time t). Speed = distance between sensors divided by t. Datapath has a counter register and the controller FSM starts and stops it on |
| What is the controller FSM for the car speed measurement system? | States: IDLE (wait for sensor 1). TIMING (sensor 1 triggered, increment counter each clock, wait for sensor 2). DONE (sensor 2 triggered, compute speed = distance divided by count, output result). Return to IDLE. |
| What are the key differences between a timer-based design and a register-based design for delays? | Timer-based: uses a dedicated counter that counts clock cycles. Clean separation of timing logic. Register-based: uses a general register loaded with the cycle count and decremented each cycle. Both achieve same result but timer design is more modular. |
| How do you connect a datapath to a controller in RTL design? | Controller outputs connect to datapath control inputs (ld clr sel cnt). Datapath status outputs (comparator results like lt eq gt tc) connect to controller as condition inputs for FSM transitions. Clock connects to both. |
| What is the HLSM notation for loading a register? | reg := expression. Example: sum := A + B means load the sum register with the value A+B on this clock edge. This notation combines the datapath operation and register load in one HLSM action. |
| How do you implement HLSM condition sum < 5099 in hardware? | Use a 16-bit comparator with A input connected to sum register output and B input hardwired to 5099 (0001001111100011 in binary). The lt output of the comparator feeds the controller as a condition signal. |
| What does the mux2x1 component do in the Figure 5.21 datapath library? | A 2-to-1 MUX with inputs I1 and I0 and select s0. When s0=0 output Q=I0. When s0=1 output Q=I1. Used by the controller to route different data sources to the same functional unit input. |
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desto