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1.1.1
| Question | Answer |
|---|---|
| CPU | Central Processing Unit: - runs FDE cycle - brain of the device |
| ALU | Arithmetic and Logic unit: - performs arithmetic (+,-,/,*, binary shifts), - logic operations (bitwise boolean operations/comparisons (AND,OR etc)) |
| CU | Control Unit: - organises data flow in and out of the CPU - decodes instructions - sends command and control signals on buses |
| Registers | Temporarily store small amounts of data for extremely fast access |
| PC (register) | Program Counter: - Stores memory address of next instruction to be fetched/executed from main memory |
| MAR (register) | Memory Address Register: - holds any memory address about to be used by the CPU (read or write) |
| MDR (register) | Memory Data Register: - stores actual data/instruction which is read from or written to memory |
| ACC (register) | Accumulator: - stores results of calculations performed in the ALU |
| CIR (register) | Current Instruction Register: - holds current instruction being decoded/executed to avoid being overwritten - contains opcode + operand |
| Buses | Carry information around the CPU + memory |
| Data bus | - carries the binary information that makes up the information being transmitted around the CPU between processor and memory - bidirectional |
| Address bus | - carries the address of the memory location being read from or written to - unidirectional (processor to main memory) |
| Control bus | - sends command/control signals between CPU and other components - bidirectional |
| FDE cycle | Fetch - Decode - Execute Cycle: - processes data - constantly running |
| Fetch (FDE) | PC copied to MAR Address sent on address bus to main memory, then waits to receive signal from control bus CU sends ‘Read’ signal on control bus to main memory Contents at memory address sent along data bus to MDR MDR copied to CIR PC incremented |
| Decode (FDE) | - CIR copied to CU - CU decodes instruction |
| Execute (FDE) | - the instruction is carried out in whatever part of CPU needed - if there was a branch, PC contents may be changed |
| Clock speed (CPU performance) | - number of FDE cycles performed per second - measured in Hertz (Hz) - 1 GHz = 1 billion per second |
| Clock period (Clock speed) | number of clock cycles per second |
| Over clocking (Clock speed) | CPU going to fast and overheating |
| Core number (CPU performance) | - each core runs independently, on different or same applications - cores still have to communicate with each other, taking time - many programs do not make use of multiple cores |
| Core (Core number) | individual processing units in a CPU chip |
| Amount of cache (CPU performance) | a higher level means faster but less capacity |
| Cache memory (Amount of cache) | - fast access memory (faster than RAM) - temporarily stores data + instructions that have been read from or written to memory, to save time |
| Von Neumann bottleneck (amount of cache) | computers overall speed limited by data transfer speed between CPU and memory |
| Instruction pipeline (pipelining) | various stages an instruction must go through (half of what processor pipeling is split into) |
| Arithmetic pipeline (pipelining) | parts of an arithmetic operation that can be broken down and overlapped as they are carried out (half of what processor pipeling is split into) |
| Flushing the pipe (pipelining) | - when a branch is found all instructions fetched and decoded in advance must be removed - slows the process |
| Pipelining | - when a core is fetching, the decode and execute sections are idle - to speed up overall execution process (NOT the individual section), the core can execute the current instruction, decode the next one, and fetch the one after that |
| Processor architecture | approach taken to a computer’s design |
| Von Neumann (processor architecture) | Older architecture Instructions and data stored in the same memory, in the same format, shares a bus Each core follows a linear FDE cycle, with only one CU and ALU One instruction at a time Registers used as fast access to instructions and data |
| Harvard (processor architecture) | Older architecture Used by RISC processors Instructions stored in program memory, data in data memory (different formats, and different buses) Instructions + data can be accessed at the same time (pro) Difficult to program (con) |
| Contemporary (processor architecture) | more modern machine architectures - Parallel processing - Distributed computing |
| Parallel processing (contemporary architecture) | processor carries out single instruction on multiple data items at the same time - often used by GPUs - SIMD (single instruction, multiple data) - MIMD (multiple instructions, multiple data) |
| Distributing computing (contemporary architecture) | multiple computers on a shared network each take on part of a bigger problem - can be done on grand scale over the internet) |
| Von Neumann (processor architecture) pros and cons | Simplifies programming (pro) Cannot read and write data at the same time (con) |
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