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Digital Electronics
Digital Electronic Circuits (Apprenticeship)
| Question | Answer |
|---|---|
| The AND operation can be produced using | Two NAND gates. Three NOR gates. |
| The OR operation can be produced using | Two NOR gates. Three NOR gates. |
| When using dual symbols in a logic diagram | Bubble outputs connect to bubble inputs. NAND symbols produce AND operations. Negative-OR symbols produce OR operations. |
| All Boolean expressions can be implemented using (Universality) | NAND gates only. NOR gates only. Combinations of NAND and NOR gates. |
| Which flip-flop has two stable states and stores one bit? | SR Flip-Flop |
| Minimum time input must be stable before clock edge (timing parameter)? | Setup Time |
| The output of an SR latch depends on | Both S and R inputs |
| Which flip-flop produces output equal to input? | D Flip-Flop |
| Input changes before setup time produce? | Setup Violation |
| JK Flip-Flop when J = K = 1 | Toggle |
| For JK FF, J = K = 0 | Same as previous Q |
| Parallel-in Serial-out register is called | PISO |
| Synchronous counters are triggered by | Clock signal |
| Which component ensures stable clock from switches? | Debouncer |
| Main advantage of asynchronous counters | Simplicity |
| Main difference between synchronous and asynchronous counters | External clock connection |
| Moore machine output depends on | Present state only |
| Mealy machine output depends on: | States and inputs |
| Likely application of an FSM: | Traffic light control |
| T Flip-Flop toggles when | T = 1 |
| In state diagrams, arrows represent | State transitions |
| Next state of D FF when D = 1 at clock edge? | 1 |
| Asynchronous counter characteristic | Ripple effect |
| Flip-flop used for toggling | T FF |
| Disadvantage of CISC architecture | Complex instruction decoding |
| Gates used to build a D Flip-Flop | NAND. NOR. |
| Technique to optimise an FSM | State minimisation using K-map |
| Propagation delay measures | Time until output is stable |
| Debouncing eliminates | Multiple triggers from a single press |
| Purpose of input in a state machine | Initiate state transitions |
| Number of outputs of a T Flip-Flop | 1 |
| Number of outputs of a D Flip-Flop | 1 |
| Number of outputs of a JK Flip-Flop | 1 |
| Number of outputs of an SR Flip-Flop | 1 |
| Logic gate used to build counters | Flip-Flop |
| Metastability refers to | Unstable output states |
| “S” in SR FF stands for | Set |
| “R” in SR FF stands for | Reset |
| Convert JK → T FF by | Connecting J and K together |
| Traffic light regulator represents | Sequential |
| Not a function of OS | Compiling programs |
| On clock edge, a D FF | Captures D |
| A Truth Table is | Table of input-output relationships |
| Logic gates used to build SR flip-flop | NAND. NOR. |
| Valid state transitions include | A → A. A → A with no input A → A with input |
| Number of inputs of a JK FF | 2 |
| Metastability refers to | Unstable state |
Created by:
user-2013151