Help
Options
Didn't know it?
click below
click below
Knew it?
click below
click below
Don't Know
Remaining cards (0)
Know
retry
shuffle
restart
0:00
Embed Code - If you would like this activity on your web page, copy the script below and paste it into your web page.
Normal Size Small Size show me how
Normal Size Small Size show me how
Module 5 Exam Prep
| Question | Answer |
|---|---|
| Instruction Sequencing | the way instructions are selected |
| Instruction Interpretation | the way instructions are executed |
| Hardwired Design | Realization of the control unit as a sequential device. |
| Micro-Programming Design | Realization of the control unit by means of programming routines |
| Microprogrammed Control Unit | simply a mechanism which allows to Store all possible output bit patterns in a memory, and read them in an orderly fashion |
| control field | used to activate functional units |
| address field | used to fetch μ-instructions in an orderly fashion |
| Horizontal instruction format | each bit of the control part represents a distinct μ-operation, Long format, Ability to express a high degree of parallelism, Little encoding of the control information |
| Vertical instruction format | control part represents just one μ-operation, Short format, No degree of parallelism, Considerable encoding of the control information |
| Diagonal instruction format | Moderate length format, Some degree of parallelism, Some encoding of the control information |
| μ-Instruction Format | F1, F2, and F3 fields are the control part(3 bits), CD is 2-bits long and defines status conditions, BR is 2-bits long and defines different types of branches, ADF is 7-bits long and represents the address field |
| Microprogrammed hardware requirements | Control store to store micro instructions, Hardware facility to fetch, decode and execute micro instructions, Mechanism to map the operation codes (at assembly level) to the proper addresses in the control store |
| Microprocessor Sequencer | It is a unit which allows to fetch the μ-instructions in an orderly fashion |
| Control unit | computer module with two major tasks: instruction sequencing and instruction interpretation. |
| Hardwired control unit | A way to design the control unit, in which the control signals are generated by random logic. |
| Micro programmed control unit | A way to design the control unit, in which the control signals are generated by reading them from the control store |
| Hardwired techniques | State table method, Delay elements method, Sequence counter method, Programmable logic array |
| In a HCU how are the control signals generated? | logic circuitry built of gates and flip-flops |
| Essentially, what is a HCU | “big decoder” |
| In a MCU instead of control signals, how does it fetch micro-operations? | The sequence of microoperations corresponding to each machine instruction is stored in a read-only memory called control ROM (CROM). The control signals are generated by decoding the microinstructions. |
| MCU Hardware requirements | -Control Store to store micro instructions. (Main memory or dedicated) -Hardware facility to fetch, decode and execute micro instructions -Mechanism to map the operation codes (at assembly level) to the proper addresses in the control store |
| MCU Flow of Control | -A macro instruction is fetched. -The operation code is mapped into a block of the control store -The designated micro instructions are fetched and executed in an orderly fashion |
| Hardwired vs. micro programmable CU, pros for MCU | MCU is more flexible because you can modify and extend the storage of machine instructions. So changes for MCU require less hardware changes |
| Hardwired vs. micro programmable CU, pros for HCU | HCUs are generally faster than MCUs and are used where the CU must be fast |
| Recent machines, MCU v HCU? | MCU |
| micro-instruction (in general) is composed to two parts | Control field, address field |
| The address field in a micro-instruction can be replaced with what? | a register called micro program counter |
| Macro instruction bits | mode bit (1), Op-code(4), operand (11) |
| ADD | ADD: NOP I CALL INDRCT READ U JMP NEXT ADD U JMP FETCH |
| BRANCH | BRANCH: NOP S JMP OVER NOP U JMP FETCH OVER: NOP I CALL INDRCT MARTPC U JMP FETCH |
| STORE | STORE: NOP I CALL INDRCT ACTMBR U JMP NEXT WRITE U JMP FETCH |
| LOAD | LOAD: NOP I CALL INDRCT READ U JMP NEXT MBRTAC U CALL FETCH |
| EXCHANGE | EXCHANGE: NOP I CALL INDRCT READ U JMP NEXT ACTMBR,MBRTAC U JMP NEXT WRITE U JMP FETCH |
| AND | AND: NOP I CALL INDRCT READ U JMP NEXT AND U JMP FETCH |
| SUB | SUB: NOP I CALL INDRCT READ U JMP NEXT SUB U JMP FETCH |
| ADM | ADM: NOP I CALL INDRCT READ U JMP NEXT MBRTAC,ACTMBR U JMP NEXT ADD U JMP EXCHANGE |
| BZ | BZ: NOP Z JMP ZERO NOP U JMP FETCH ZERO: NOP I CALL INDRCT MARTPC U CALL FETCH |
| SEQ | SEQ: NOP I CALL INDRCT READ U JMP NEXT MBRTAC,ACTMBR U JMP NEXT SUB U JMP NEXT MBRTAC,ACTMBR Z JMP EQUAL NOP U JMP FETCH EQUAL: INCPC U JMP FETCH |
| BPNZ | BPNZ: NOP S JMP FETCH NOP Z JMP FETCH NOP I CALL INDRCT MARTPC U JMP FETCH |
| FETCH | FETCH: PCTMAR U JMP NEXT READ,INCPC U JMP NEXT MBRTMAR U MAP |
| μ-Instruction Format | F1 (3), F2 (3), F3 (3), CD (2), BR (2), ADF (7) |
| F1-F3 in μ-Instruction Format | control fields, each has a separate table of micro operations that the 3 bits decodes into |
| CD in μ-Instruction Format | conditions: U,I,S,Z |
| U condition | No condition |
| I condition | Indirect mode |
| S condition | sign of AC |
| Z condition | if AC = 0 |
| BR in μ-Instruction Format | Branches/Branching |
| ADF in μ-Instruction Format | address field, tells you where to branch to |
| BR modes | 00 or JMP 01 or CALL 10 or RET 11 or MAP |
Created by:
kjw6m7