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Computer Systems
University Computer Systems
| Question | Answer |
|---|---|
| What does a CPU do? | Fetches, decodes and executes program instructions. |
| What are the two principal parts of the CPU? | Datapath and control unit |
| What does the datapath consist of? | Arithmetic-logic unit and storage units(registers) |
| How are registers and arithmetic-logic unit connected to each other and to the main memory? | Via a data bus |
| What does the control unit do? | Sends signals to tell the various components within the CPU to perform sequenced operations. And determines which actions to carry out according to the values in the program counter register and a status register. |
| What are registers for? | To hold data that can be readily accessed by the CPU |
| How many D flip-flops does a 32-bit register need? | 32 D flip-flops |
| What does the airthmetic-logic unit do? | Carries out logical and arithmetic operations as directed by the control unit |
| What does computer memory consists of? | Linear array of addressable storage cells that are similar to registers. |
| What are the different memory addressable types? | byte addressable and word addressable (word typically consists of two or more bytes. |
| What is RAM also referred to in terms of? | length x width RAM (4M x16 RAM, 4 megabytes of 16 bit memory locations) |
| How many words can be expressed from 4M? | 2^2 x 2^20 = 2^22 words that can be expressed with 4M |
| What are the memory locations numbered from in 4M memory? | 0 to 2^22 -1 |
| How many address lines in a memory bus is required to access 4M memory? | at least 22 address lines |
| What are the two different ways I/O devices can connect to the CPU? | Memory-mapped and instruction-based |
| What is memory-mapped interface? | Where the I/O device behaves like main memory from the CPU's point of view. |
| What is instruction-based interface? | Where the CPU has a specialised I/O instruction set. |
| How does the CPU share data with ohter system components? | Through the data bus. |
| What is a bus? | It is a set of wires that simultaneously convey a single bit along each line. |
| What are the two types of buses commonly found in computer systems? | Point-to-point and multi-point buses. |
| What do buses consists of ? | Data lines, control lines and address lines. |
| What do data lines in a bus do? | convey bits from one device to another. |
| What do control lines in a bus do? | determine the direction of data flow and when each device can access the bus. |
| What do address lines in a bus do? | determine the data source or destination location. |
| What is point-to-point bus? | One component is connected to another component in a linear fashion. |
| What is a multi point bus? | Its where the bus is a shared resource and access to it is controlled through protocols that determine how devices can use it. |
| What is a master-slave configuration? | Its where more than one device can be the bus master, concurrent bus master requests must be arbitrated (reach an authoritative judgement) |
| What does arbitration mean? | It means to meat an authoritative judgement or settlement. |
| What are the four categories of bus arbitration? | Daisy chain Centralised parallel distributed using self-detection Distributed using collision detection |
| What is daisy chain bus arbitration? | When permissions are passed from the highest priority device to the lowest in a bus. |
| What is centralised parallel bus arbitration? | When each device is directly connected to an arbitration circuit. |
| What is distributed using self-detection bus arbitration? | When devices decide which gets the bus among themselves. |
| What is distributed using collision detection bus arbitration? | When any device can try to use the bus. If its data collides with the data of another device it tries again. |
| What does every computer need to synchronise the activities of its components? | At least one clock |
| What is required to carry out each data movement or computational operation in terms of the clock? | A fixed number of clock cycles. |
| What is clock frequency? | Its measured in megahertz or gigahertz and determines the speed with which all operations are carried out. |
| How do you work out cycle time? | the reciprocal of clock frequency. (600MHz has a cycle tiime of 1.25 ns) |
| What does clock speed not relate to? | The CPU performance. |
| What increases the CPU general performance? | reducing the number of instructions in a program. reducing the number of cycles per instruction. reducing the number of seconds per clock cycle. |
| What do interrupts do? | They allow normal execution of a program to be altered/stopped in an event of higher-priority occurs. |
| What can trigger a interrupt? | I/O requests arithmetic errors ( such as division by zero) encountering invalid instructions |
| What does MARIE stand for? | Machine Architecture that is Really Intuitive and Easy |
| What data representation does MARIE use? | two's complement data representation. |
| What features does stored data and instructions have in MARIE? | fixed worth length data and instructions |
| How many words of word-addressable main memory does MARIE have? | 4K words of word-addressable main memory (2^2 * 2^10 = 2^12) |
| What bit data words does MARIE use? | 16 bit data words. |
| What are the features of the instructions that MARIE uses? | 16-bit instructions, 4 for op code and 12 for the address. |
| What bit is the arithmetic logic unit? | 16 bit. |
| How many registers does MARIE have for control and data movement? | seven registers |
| What are MARIE's seven registers in words? | Accumulator Memory address register Memory buffer register Program counter Instruction register Input register Output register |
| What are MAIRE's seven registers in short hard letter form? | AC MAR MBR PC IR IN OUT |
| What does the accumulator do? | holds a conditional operator (e.g less than) or operand of a tow-operand instruction |
| What does memory address register do? | holds the memory address or operand of an instruction. |
| What is operand of an instruction? | The data that is to be operated on (e.g the address of it) |
| What does the memory buffer register do? | holds data after retrieval from, or before placement in memory. |
| What does the program counter do? | Holds the address of the next program instruction to be executed. |
| What does the Instruction register do? | holds an instruction immediately preceding its execution (before execution) |
| What does the Input register do? | holds data read from an input device. |
| What does the input register do? | hold data that is ready for the output device. |
| How many bits does MARIE's accumulator have? | 16 bits |
| How many bits does MARIE's memory address register have? | 12 bits |
| How many bits does MARIE's memory buffer register have? | 16 bits |
| How many bits does MARIE's program counter have? | 12 bits |
| How many bits does MARIE's Instruction register have? | 16 bits |
| How many bits does MARIE's input register have? | 8 bits |
| How many bits does MARIE's output register have? | 8 bits |
| What is the last address for MARIE | 4095 as it has 4K words of word-addressable memory so it has 2^2 * 2^10 word locations = 2^12 word locations. And locations are numbered to 0 to 2^12 -1. |
| How are registers connected with main memory in MARIE? | Through a common data bus. |
| How does each device get identified on the bus and where/when does the identification get set in MARIE? | It's identified by a unique number. The number is set on the control lines whenever the corresponding device is required to carry out an operation . |
| Where are there separate connections in MARIE? | Between the accumulator and the memory buffer register. Between the Arithmetic Logic unit and memory buffer register |
| What is the purpose of separate connections between AC and MBR and ALU and MBR in MARIE? | So that data can transfer between these devices without using the main data bus. |
| Whats is ISA stand for? | instruction set architecture |
| What does instruction set architecture specify? | The format of its instructions and the primitive operations that the machine can perform. |
| What is an instruction set architecture? | an interface between a computer's hardware and its software and they include instructions for processing data and controlling program execution. |
| How many instructions does the MARIE ISA consists of? | 13 |
| In MARIE ISA what does Skipcond do if 00? | skip if AC <0 |
| In MARIE ISA what does Skipcond do if 01? | skip if AC =0 |
| In MARIE ISA what does Skipcond do if 10? | skip if AC > 0 |
| What do instructions consist of ? | A sequence of smaller instructions called micro-operations. |
| What can the exact sequence of micro-operations that are carried out by an instruction be specified by uisng? | register transfer language (RTL) |
| What does RTL stand for | register transfer language. |
| What does M[X] ← Y mean in MARIE RTL? | It means the value Y is transferred to the memory location of X. |
| What is this the MARIE RTL for? MAR←X MBR←M[MAR] AC←MBR | It is the RTL for the LOAD instruction. |
| What is this the MARIE RTL for? MAR←X MBR←M[MAR] AC←AC+MBR | It is the RTL for the ADD instruction |
| What happens in the fetch part of CPU cycle? | The PC is copied to the MAR then the contents of the memory at address MAR to IR. Then the PC is incremented by 1 |
| What happens in the decode part of CPU cycle? | Once in the IR decode the instruction (opcode) and place the memory part of instruction in the IR to the MAR |
| What happens when an operand is involved in an operation? | It is retried from using the address in the MAR and placed into the MBR |
| When does an interrupt occur? (3 different ways) | A user break. I/O is requested by the user or a program. A critical error. |
| What are software interrupts also known as? | traps |
| What does interrupt processing involve? | Adding another step to the fetch-decode-execute cycle. |
| What happens when a interrupt signal is detected? | You save the variables and registers. Then look up ISR (interrupt service routine) address in interrupt vector table. Then place ISR address in PC Finally branch to ISR to start executing ISR |
| What happens after an interrupt has finished? | You restore saved registers and variables then branch back to top of fetch-decode-execute cycle |
| In general-purpose systems what is it common to do for interrupts? | to disable all interrupts during the time in which an interrupt is being processed. |
| How can disabling all interrupts during an interrupt be achieved? | By setting a bit in the flags register |
| What are interrupts that are ignored by flag register bit? (for disabling interrupts) | Maskable |
| What are interrupts that must be processed in order to keep the system in a stable condition called? | Nonmaskable interrupts |
| How does MARIE get input from IN? | The CPU polls the input register, IN until input is sensed which is when the value is then copied into the accumulator. |
| How does MARIE output? | All output is placed in an output register, OUT. |
| What bit index range will be used in MARIE to store in MAR? (inclusive) | 11-0 |
| What bit index range will used in MARIE to get the opcode from the IR? (inclusive) | 12-15 e.g (Decode IR[15-12]) |
| What are Mnemonic instructions and will a computer use it?Why? | Such as Load 104, easy for humans to write and understand but impossible for computer to understand |
| What are assemblers? | translates instructions that are comprehensible to humans into machine language that is comprehensible to computers |
| What is the different between assemblers and compilers? | For assembly language it is usually a one-to-one correspondence between instruction and its machine code. Compilers, this is not usually the case (multiple lines of machine code). |
| What does a Assemblers create ? | creates an object program file from mnemonic source code |
| What does the assembler do in its first pass? | assembles as much of the program as it can. While it builds a symbol table that contains memory references for all symbols in the program. |
| What does the assembler do in its second pass? | the instructions are completed using the values from the symbol table. |
| What does radix mean? | The term used to describe the number of digits used before rolling over to next digits place (e.g hexadecimal or decimal base 10) |
| What is direct addressing? | The address of the operand is explicitly stated in the instruction |
| What is indirect addressing? | This is where the address of the address of the operand is given in the instruction. Like pointers |
| What are MARIE's extended instruction set for indirect address mode instructions? | AddI JnS JumpI |
| What does MARIE's AddI do? | Add a value at address in address specified (uses an address to get the data at the address that is stored in the initial address) |
| What does MARIE's JnS do? | Jump to subroutine at specified address |
| What does MARIE's JumpI do? | Jump to the address in the address specified. |
| How do you zero the accumulator in MARIE? | Clear |
| How does JnS operate/work? | Starts by storing the current PC value in the first address of the routine itself, then by continuing with the instruction following that by storing the entry address +1 in the PC |
| What is RTL for MARIE Clear? | AC←0 |
| What does ISA stand for? | Instruction set architecture |
| What are the 6 different factors to consider when looking at different ISAs? | Instruction Length. Number of explicit operands per instruction. Type,size and location of operands. Memory organisation (byte or word addressable) Addressing modes ( direct, indirect or indexed) Types of operations available. |
| When choosing an ISA what are the 3 main measures we care about? | Main memory space occupied by a program. Instruction complexity and length(in bits). Total number of instructions in the instruction set. |
| What does endianness refer to? | Endianness refers to the sequential order used to numerically interpret a range of bytes in computer memory as a larger, composed word value. (how to read larger numbers with multiple bytes) |
| What is Byte ordering also referred to as? | Endianness |
| What is little endian? | When the least significant byte is followed by the most significant bit. 12345678 will be stored 78 56 34 12 |
| What is big endian? | When the most significant byte is followed by the least significant byte. 12345677 will be stored 78 56 32 12 |
| What are the benefits of Big endian? | Its more natural. Sign can be determined by byte at address offset 0 (first). Strings and integers are stored in the same order. |
| What are the benefits of little endian? | Makes it easier to place values on non-word boundaries. Conversion from 16-bit integer address to 32-bit one does not require any arithmetic |
| What are the 3 types of design choices for how the CPU will store data? | Stack architecture. Accumulator architecture. A general purpose register architecture. |
| What are the trade offs between the different designs of how CPU will store data? | Simplicity and cost of hardware design. execution speed and ease of use. |
| How does the stack architecture work? | They are implicitly taken from the stack (no random access) |
| How does the accumulator architecture work? | one operand of binary operation is implicitly in the accumulator (creates lots of bus traffic as one operand is in the memory only) |
| What does GPR stand for? | General purpose register |
| How does the GPR architecture work? | registers can be used instead of memory. |
| How is GPR arcitecture better and worse than accumulator architecture? | GPR is faster but it require longer instructions |
| What type of architectures are most systems? And what are the three types? explain each | GPR 1)Memory-memory where two or three operands may be in memory 2)Register-memory where at least one operand must be in a register 3)Load-Store where no operand may be in memory |
| What directly affects the instruction length? | number of operands and the number of available registers |
| What types of operand instructions do stack machines use? | one- and zero-operand instructions |
| What do binary instructions use in a stack machine? | the top two items on the stack. |
| How many memory addresses does a stack machine need for push and pop operand? | a single memory address |
| What is infix notation? | Notation that we are used to like Z = X + Y |
| What is postfix notation? | Reverse polish notation where it can be calculated using a stack machine e.g Z = X + Y would be Z = XY+ in postfix notation |
| What is the advantage of postfix notation? | Parentheses are not needed as Z = (X * Y) + (W * U) can be written in postfix notation as Z = XY * WU * + |
| What specifies where an operand is located? | the addressing modes of the operand |
| What is the actual location of an operand called? | The effective address |
| What are the 8 different addressing types? | Immediate Direct Register Indirect Register indirect Indexed Based Stack |
| What is immediate addressing? | When the data is part of the instruction |
| What is direct addressing? | When the address of the data is given in the instruction |
| What is register addressing? | When the data is located in a register |
| What is indirect addressing? | When the address of the address of the data is given in the instruction |
| What is register indirect addressing? | When it uses a register to store the address of the address of the data |
| What is indexed addressing? | When it uses an indexed register (implicitly or explicitly as an offset), which is added to the address in the operand to determine the effective address of the data |
| What is based addressing? | When it uses a base register (implicitly or explicitly as an offset), which is added to the address in the operand to determine the effective address of the data. |
| What is the difference between index and based registers? | The number of bits that represent the constant that is added to find the address. And an index register has an offset from the address but the base register holds a base address and address field is a displacement from the base. |
| What is parallel execution of smaller steps called? | Instruction-level pipelining |
| What is the theoretical speed up offered by instruction-level pipelining? | Time for first task to complete +( (the number of tasks in program -1)*time taken for a single stage) T=Kt+ (N−1)t as every task after the first will be complete each stage |
| What is the formula to calculate fractional speed gain? | Time without pipelining / Time with pipelining NKt / (K +N -1)t |
| If the number of tasks tend towards infinity what is the theoretical speed up of pipelining? | K (the amount of stages in the pipeline) (K + N -1) tends towards N so Speed = Kt/t = K |
| What do the pipelining equations assume? | The architecture supports fetching instructions and data in parallel. The pipeline can be kept filled at all times. |
| What is a pipeline hazard? | Something that causes a pipeline to stall, or be flushed. |
| What are 3 examples of a pipeline hazard? | Resource conflicts Data dependencies Conditional branching |
| What is the formula for basic CPU time? | seconds per program = instructions per program * average cycles per instructions * seconds per cycle |
| CPU efficiency is a factor to the overall system performance what are two other factors? | Memory and I/O performance |
| What do we need to use examine overall performance? | Amdahl's Law |
| What does the symbol φ represent in Amdahl's Law ? | the fraction of work done by the component. |
| What does CPU, Memory or I/O bound mean? | It means it's slowing down the overall speed of a system. |
| If CPU, Memory or I/O is bound what is needed in order to speed up the overall system? | Upgrade the part that is bound. |
| What is the formula to calculate the execution time of a system with new component installed? | Time taken for fraction of work not done by component + time taken for the fraction of work done by component (1−φ)T+(φ/Component Speed up)T |
| What is the formula for the overall fractional speed up of a system with new component? | 1/(1− φ + (φ / (Component Speed up))) |
| Why are early synthetic benchmarks like Linpack, Dhrystone and Whetstone no longer used? | They are relatively small programs and so are too easy to optimise for and too small to be useful. |
| What does SPEC stand for? | Standard Performance evaluation corporation. |
| What does ISA stand for? | Industry standard architecture |
| Why was SPEC formed? | to address the need for objective benchmarks |
| What two parts are contained in SPEC CPU benchmark? | CINT2017 and CFP2017 |
| What does CINT2017 do? | Measures integer arithmetic operations |
| What does CFP2017 do? | Measures floating point processing |
| What do SPEC benchmarks consist of ? | Collection of kernel programs. These are programs that carry out the core processes involved in solving a particular problem and activities that do not contribute to solving the problem such as I/O are removed. |
| How many applications are in CINT2017? | 10 applications |
| How many applications are in CFP2017? | 13 applications |
| What are programming languages are SPEC benchmarks programmed in? | A mixture of FORTRAN, C and C++ |
| What is the end result of the SPEC benchmarks? | A geometric mean of all the run times. the execution for each kernel is divided by the run time for the same kernel on a historical Sun Fire V490 with 2100MHz UltraSPARC-IV+ chips. |
| What two numbers may manufactures report from SPEC benchmarks? | the peak and base numbers are the results with and without compiler optimisation flags, respectively. |
| What are some ways to achieve CPU optimisation? | pipelining, parallel execution units, integrated floating-point units, RISC vs CISC ISA design and branch optimisation |
| What are the two main kinds of ISA designs? | RISC and CISC |
| What does RISC stand for? | Reduced instruction set computers |
| What does CISC stand for? | Complex instructions set computers |
| What type of systems use RISC or CISC? | Von neumann systems. |
| What do RISC systems do for performance? | shorten execution time by reducing the clock cycles per instruction |
| What do CISC systems do for performance? | improve performance by reducing the number of instructions per program |
| What type of instructions do RISC machines have? | few, simple instructions fixed in length |
| What can you do with control units in RISC? | can be hardwired for maximum speed. |
| How do the number of cycles to process instructions vary in RISC? | they have the same number of cycles which makes it easier to manage and form pipelines |
| What is the problem with RISC? | programming is harder, requires more instructions for complex operations. |
| What features does RISC memory accessing have? | Only Load/Store and few addressing modes. |
| What is a benefit and drawback with RISC's memory management? | + parameter passing through registers makes it fast sequential execution -requires more (expensive) CPU registers |
| What type of instructions do CISC machines have? | Many complex instructions of variable length. |
| What is the problem with control units in CISC? | they must use special circuits to interpret instructions as they are fetched from memory and this can take time;. |
| What is it about the instructions in CISC that make it worse than RISC? | As instructions can have multiple/variable number of cycles to process it make it harder to manage and from pipelines. |
| What is good about CISC instructions? | Easier to program and fewer instructions are needed for complex operations. |
| What features does CISC memory accessing have? | Many instructions can access memory and there are many addressing modes. |
| How are parameters passed through in CISC and what is the downside of that? | through memory which can be a bottlneck |
| What is the benefit of CISC memory management? | Fewer registers are needed and fewer operands per instructions. |
| What is branch optimisation? | It is the dealing with pipeline hazards to improve parallelisation |
| What is delayed branching? | One or more instructions following a conditional branch are sent down the pipeline regardless of the outcome of the statement |
| What is branch predication? | When a guess is made as to what will be the next instruction (speculative execution) |
| What is Optimal disk performance critical for? | system throughput ( amount of data passing through a system) |
| What is the speed of Disk drives compared to main memory? | one million times longer accesses times |
| What is wrong with disk drive systems? | a slow disk system can choke transaction processing and drag down the performance of all programs. |
| What does low CPU utilisation indicate? | problem in the I/O subsystem because the CPU spends more time waiting than running. |
| What is disk utilisation? | the percentage of time that the disk is bust servicing I/O requests and gives the probability that the disk will be bust when another I/O request arrives in the disk service queue. |
| What does disk utilisation depend on? | the speed of the disk and the rate at which requests arrive in the service queue. |
| What is the equation for disk utilisation? | request arrival rate / disk service rate = (requests per second) / (I/O operations per second) |
| What is the time a request spends in a queue directly related to? | the service time and the probability that the disk is busy. |
| What is the time a request spends in a queue inversely related to? | the probability that the disk is idle. |
| What is the 'knee' of the curve for disk performance ( disk queue time in seconds over utilisation percentage) ? | around 78% |
| What is the rule of-thumb upper limit for utilisation for most disk drives? | 80% |
| What affects throughput ? | The way files are organised on a disk The average seek time Disk scheduling algorithms to minimise seek time |
| Why does file organisation affect throughput? | as disk arm motion is the greatest consumer of service time |
| What does FCFS stand for? | First come first served |
| What does FCFS disk scheduling do? | I/O requests are serviced in the order which they arrive. |
| What is the benefit of FCFS disk scheduling? | Simple to implement |
| What is the downside of FCFS disk scheduling? | No real control over arm motion. and therefore performance is unpredictable and widely variable. |
| What does SSTF stand for? | shortest seek time first |
| What does SSTF disk scheduling do? | I/O requests are ordered according to the arm motion needed to service the request. |
| What is the benefit of SSTF disk scheduling? | Disk arm moves only to the track nearest its current location time reducing seek time. |
| What is the drawback of SSTF disk scheduling? | More complex to implement and starvation is possible. |
| What is Starvation in terms of disk scheduling? | when an I/O requests is mode for remote track and this request will keep getting shoved to the back of the queue while nearer requests are serviced. |
| What is a way of preventing starvation in terms of disk scheduling? | having the disk arm continually sweep over the whole surface of the disk. |
| What is SCAN disk scheduling? | I/O requests are serviced according to track distance with a scan to the edge of the disk enforced. |
| What is the benefits of SCAN disk scheduling? | It ensures fairness. Motion is constant and predictable Arm changes direction only twice. At the centre and at the outermost edges of the disk. |
| What is the drawbacks of SCAN disk scheduling? | A lot of arm motion is needed complex implementation |
| What is circular SCAN (C-SCAN) disk scheduling? | I/O requests are serviced according to track distance, a scan to the edge of the disk enforced, and then a scan to the first track of the disk is enforced. |
| What is the benefit of C-SCAN disk scheduling? | arm only moves in one direction so simpler to implement than SCAN |
| What is the down side of C-SCAN disk scheduling? | Arm motion to first track is wasteful. |
| What is the difference between LOOK and SCAN disk scheduling? | Disk arm only travels to the highest and lowest numbered tracks for which access requests are pending. |
| What is the benefit of LOOK disk scheduling? | They provide the best theoretical throughput and reduce the arm motion. |
| What is the down side of LOOK disk scheduling? | The circuitry is the most complex out of all the disk scheduling. |
| At high utilisation which disk scheduling performs better but what is downside? | SSTF but still has risk of starvation. |
| At very low utilisation (under 20%) what types of disk scheduling is acceptable? | any of he algorithms. |
| Where should most frequently-used files reside? | in the centre tracks of the disk and should be periodically defragmented. |
| What is the best way to reduce disk arm motion? | to avoid using the disk as much as possible by using cache memory or main memory set aside for the exclusive use of the I/O subsystem |
| What do many disk caches use to reduce disk accesses? | Prefetching |
| What is prefetching in terms of disk caches? | when a number of sectors subsequent to the one requested are read with the hope that some of them will be needed 'soon' |
| What is the problem with prefetching in caches? | It can cause cache pollution |
| What is cache pollution? | when the cache is filled with data that no process needs, leaving less room for useful data. |
| What can be used to keep the cache clean from pollution? | Replacement algorithms like LRU, LFU and random |
| What is the problem with cached disk writes? | cache is volatile memory so in the event of a system failure, data in the cache will be lost. Which is bad if an application believes data has been committed to disk when its really just in the cache. |
| What is done to defend against power loss to the disk cache? | some disk caches are mirrored and supplied with a battery backup |
| What is write-through cache? | When a copy of the data is retained in the cache and simultaneously written to the disk. |
| What is the benefit of write-though cache? | improves reliability |
| What is the drawback of write-though cache? | reduces performance |
| When throughput is more important that reliability what may a system employ for the cache? | write back caching or opportunistic writes |
| What is write back caching? | where dirt blocks are periodically written back to disk. |
| What is opportunistic writes? | dirty blocks wait in the cache until the arrival of a read request for the same cylinder. The write operation is then 'piggybacked' onto the read operation |
| What is the benefit of write back caching? | It improves write performance |
| What is the drawback of write back caching? | reduces performance for reads |
| What is our first responsibility for optimising disk performance? | To ensure data reliability and consistency |
| Is it better to upgrade disk subsystem or just replace lost data and why? | Upgrade sub system as its always cheaper than replacing lost data. |
| What do humans typically use for representing numbers? | decimal system |
| What is the decimal system also known as? | Base-ten number system |
| What do computers typically use for representing numbers? | Binary |
| What type of number system is binary? | base-two number system |
| What do we use to distinguish between numbers in different bases? | radix notation |
| What is a group of 8 bits called? | a byte |
| What is a group of 4 bits called? | nybble/nibble |
| What is a nybble? | a group of 4 bits |
| What is a byte | a group of bits |
| What are two ways to convert decimal numbers to other bases? | subtraction and division-remainder |
| What can you use to work out the max value of n bits can represent? | 2^n -1 |
| What is the subtraction method for converting decimal numbers to binary? | Do repeated subtractions starting from the highest power and if we do a subtraction from that power we write 1 else we write 0 |
| How does the division remainder method work for converting decimal numbers to binary? | You do long division of the number you want to convert divided by the radix you want to convert into then the remainder will be placed at that place then this is done till you have nothing to divide. Then you read it bottom to top |
| How do you convert fractional decimal components to binary using subtraction? | Do repeated subtractions starting from the power -1. If you make a subtraction for a power then you write 1 at that position if not then you write 0. |
| Why can you not always accurately convert fractional components to other bases? | Because some times there isn't a exact representation of the fraction in that number system. |
| What can unsigned binary not do? | represent negative values. |
| What are 3 formats that can represent negative values? | Signed magnitude One's complement Two's complement |
| What is signed magnitude binary format? | When you assume the most significant bit (MSB) is a sign bit that represents the sign of the number. If MSB = 0 then positive If MSB =1 then negative The rest is interpreted as unsigned binary (magnitude) |
| What is 01101 in signed magnitude? | +13 |
| What is 11011 in signed magnitude? | -11 |
| What is the advantages of signed magnitude? | It is simple and intuitive. It is easy to convert unsigned values to positive signed values |
| What is the disadvantage of signed magnitude? | It's difficult to perform arithmetic. there are two representations of 0 (positive zero and negative zero) |
| How does one's complement represent binary numbers? | First you convert a decimal into a binary then add zeros (to the front) until you have the bits you want to represent the binary number with If it is negative then you flip all the digits else you just leave it |
| What is -14 base 10 in one's complement binary using 5 bits? | 10001 |
| How do you convert a binary one's complement number to decimal? | If the MSB is 1 then we know it's negative and then flip all bits if it is negative. Then convert as unsigned binary |
| What is the advantage of One's complement binary representation? | Addition using one's complement is easy, therefore simple circuits |
| What are the disadvantages of One's complement binary representation? | There are two representations of 0 (positive zero and negative zero) |
| What is the binary representation format of Two's complement? | In two's complement the MSB is a negative value so if it starts with 0 then it is positive. |
| What is the advantages of Two's complement? | No bits with special meaning, therefore simple circuits (same hardware can be used to perform both signed and unsigned arithmetic) There is a single representation of zero |
| What is the disadvantage of Two's complement? | There are none. |
| Why is two's complement the most widely used format today? | There are no disadvantages. |
| Why so we use hexadecimal numbers? | As when binary numbers get moderately large they become very difficult to read for humans and binary makes it a lot easier to read larger values. |
| What base is hexadecimal? | base -16 |
| What do you use for the other six characters in hexadecimal? | Letters from A-F where A = 10 |
| How do you convert binary number to hexadecimal? | You group binary number into groups of 4 bits(nybbles) Then convert each separate nybble to decimal Each nybble now translates to one hexadecimal character |
| What is another notation of the hexadecimal number AFF3? | 0xAFF3 using prefix 0x |
| Why do computers use binary? | Because of properties of physical hardware that is currently used. Transistors that have an on and an off state map easily to 1 and 0. Moreover it is efficient for computing the logic of computation |
| Why wont quantum computers not use binary number system? | As they will use 'Qubits' which will have varying number of states so it will use quantum logic and not Boolean logic |
Created by:
Roobobster