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ch.5 Study Notes
| Question | Answer |
|---|---|
| Uses set of general-purpose registers, are the most widely accepted modules for machine architectures today. registers sets are faster than easier for compilers to deal with | General- purpose register architectures |
| An instruction design that allows the opcode to vary in the length, dependent on the number of operands required for the instruction. | Expanding Opcode |
| Most UNIX machines are what? | Big Endian |
| Stores the same two-byte integer with the most significant byte first, followed by the least significant byte. -Stores the most significant bytes at the lower addresses | Big Endian |
| This is the most basic means to differentiate ISA(interal storage architecture). There are three choices: | 1. A stack architecture 2. An accumulator architecture 3. A general-purpose registers (GPR) architecture |
| It has only one operand implicitly in the accumulator, minimize the internal complexity of the machine and allow for very short instructions. -it is only temporay storage -memory traffic is very high | Accumulator Architectures |
| Use a stack to execute instructions, and the operands are (implicitly) found on top of the stack. | Stack architectures |
| Some machines store a two-byte integer,for example, with the least significant byte first (at the lower address), followed by the most significant byte -A byte at a lower address has lower significance | Little endian |
| Most newer RISC(reduced instruction set computer) architectures are what? | Big Endian |
| Computer architecture's "byte order" or the way the computer stores the bytes of a multiple-byte data element. | endian |
| May have two or three operands in memory, allowing an instruction to perform an operation without requiring any operand to be in a register. | Memory-memory architectures |
| Requires a mix, where at least one operand is in register and one is in the memory | Register-memory architectures |
| Requires data to be moved into registers before any operations on those data are performed. | Load-store architectures |
| Intel and Motorola are examples of this: | Register-memory architectures |
| Digital Equipment's VAX architecture allows this: | memory-memory architectures |
| SPARC, MIPS,Alpha and the PowerPC are all what? | Load-Store machines |
| Wastes space but is fast and results in better performance when instruction-level pipelining is used. | Fixed Length |
| More complex to decode but saves storage space. | Variable Length |
| A mathematical notation made it possible by logician Jan Lukasiewicz, a polish mathematician who invented this notation in 1924. | Reverse Polish Notation (RPN) |
| The representation that places the operator after the operands -Ex:XY+ | Postfix Notation |
| Places the operator between operands -Ex:X+Y | Infix Notation |
| Places the operator before the operands -Ex:+XY | Prefix Notation (Polish) |
| It represents a compromise between the need for rich set of opcode and desire to have short opcodes, and thus short instructions. | Expanding opcode |
| An instruction set is said to be orthogonal if the instructions are independent (there is no overlap in functionality)and consistent (there are no special registers, all addressing modes can be used with any data type or instruction type, instructions hav | Orthogonality |
| Allows us to specify where the instruction operands are located | Addressing modes |
| Is so named because the value to be referenced immediately follows the operation code in the instruction. | Immediate addressing |
| Is so named because the value to be referenced is obtained by specifying its memory address directly in the instruction. | Direct addressing |
| a register, instead of memory, is used to specify the operand. | Register addressing |
| is a powerful addressing mode that provides an exceptional level of flexibility. | Indirect addressing |
| works exactly the same way as indirect addressing mode. | Register indirect addressing |
| mode, an index register (either explicitly or implicitly designated) is used to store an offset (or displacement), while is added to the operand, resulting in effective address of the data. | indexed addressing |
| mode is similar to indexed addressing, except a base address register, rather than an index register is used. | Based addressing |
| if used, the operand is assumed to be on the stack. | stack addressing mode |
| used both indirect and indexed addressing at the same time. | indirect indexed addressing |
| which adds an offset to a specific base register and then adds this to the specific operand, resulting in the effective address of the actual operand to be used in the instruction. | base/offset addressing |
| automatically increment the register used, thus reducing the code size, which can be extremely important in applications such as embedded systems. | auto-increment |
| automatically decrement the register used, thus reducing the code size, which can be extremely important in applications such as embedded systems. | auto-decrement |
| computes the address of the operand as an offset from the current instruction. | Self-relative addressing |
| The process of breaking down the fetch-decode-execute cycle into smaller steps (pipeline stages), where some of these smaller steps can be overlapped and performed in parallel | Pipelining |
| Each step in a computer pipeline completes a part of an instruction is called | pipeline stage |
| (also called structural hazards) are a major concern in instruction-level parallelism. | Resource conflicts |
| (also called resource conflicts) are a major concern in instruction-level parallelism | structural hazards |
| arise when the result of one instruction, not yet available, is to be used an an operand to a following instruction. | Data dependencies |
| Many architectures offer this, using logic to make the best guess as to which instructions will be needed next (essentially, they are predicting the outcome of a conditional branch). | branch prediction |
| Compilers try to resolve branching issues by rearranging the machine code to cause ____________. | delayed branch |
| The limits of dynamic scheduling have led machine designers to consider a very different architecture, _______________, exemplified by the Itanium architecture. | Explicitly Parallel Instruction Computers (EPIC) |
| To reduce the pipelining problems caused by conditional branches, the IA-64 introduced ________________. | predicated instructions |
| architectures combine superscalar concepts with pipelining by dividing the pipeline stages into smaller pieces. | Superpipelining |
| means each instruction can specify multiple scalar operations (the compiler puts multiple operations into a single instruction). | VLIW (very long instruction word)architecture |
| is a software emulation of a real machine. | virtual machine |
| is essentially a "wrapper" that goes around the hardware architecture and is very platform dependent. | Java Virtual Machine (JVM) |
| are produced when a Java program is compiled. | Bytecodes |
| Languages that are a bit of both (compiled and interpreted). | P-code language |
Created by:
kanesha.thomas