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PLTW sudy
Question | Answer |
---|---|
flip-flop | A sequential circuit based on a latch whose output changes when its CLOCK input receives a pulse. |
level sensitive | Enabled by a logic HIGH or LOW level. |
Duty Cycle | Fraction of the total period that a digital waveform is in the HIGH state. |
Clock | Digital signal in the form of a rectangular pulse train or a square wave. |
Asynchronous Counter | Type of counter in which each flip-flop output serves as the clock input signal for the next flip-flop in the chain. |
edge sensitive | Manner in which a flip-flop is activated by a signal transition |
Trigger | Input signal to a flip-flop or one-shot that causes the output to change states depending on the conditions of the control signals. |