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com 1
| Question | Answer |
|---|---|
| Virtually all contemporary computer designs are based on concepts developed by | John von Neumannat (the Institute for Advanced Studies, Princeton.) |
| A sequence of codes or instructions is called | software. |
| The processing required for a single instruction is called a(n) | instruction cycle. |
| a __generated by a failure such as power failure or memory parity error | hardware failure |
| a ___generated by some condition that occurs as a result of an instruction execution. | program |
| A bus that connects major computer components (processor, memory, I/O) is called a | System bus. |
| ___ are used to designate the source or destination of the data on the data bus. | The address lines |
| The data lines provide a path for moving data among system modules and are collectively called the | data bus. |
| A ___ is the high-level set of rules for exchanging packets of data between devices. | Protocol |
| Each data path consists of a pair of wires (referred to as a ___) that transmits data one bit at a time. | lane |
| ___receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. | Transaction Layer |
| ___is used to determine the course that a packet will traverse across the available system interconnects. | The QPI routing layer |
| A ___ specifies the address in memory for the next read or write. | memory address register (MAR) |
| A ___ contains the data to be written into memory or receives the data read from memory. | memory buffer register (MBR) |
| The most common classes of interrupts are: program, timer, I/O and | hardware failure |
| A(n) ___ is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis. | timer interrupt |
| A(n) ___ is generated by an I/O controller to signal normal completion of an operation, request service from the processor, or to signal a variety of error conditions. | I/O interrupt |
| A ___ simply means that the processor can and will ignore that interrupt request signal. | disabled interrupt |
| The collection of paths connecting the various modules is called the | interconnection structure. |
| A ___ is a communication pathway connecting two or more devices. | bus |
| The ___ lines are used to control the access to and the use of the data and address lines. | control |
| There are three important groups of DLLPs used in managing a link: flow control packets, ___, and TLP ACK and NAK packets. | power management packets |
| The purpose of the PCIe ___ layer is to ensure reliable delivery of packets across the PCIe link. | data |
| With ___ transmission signals are transmitted as a current that travels down one conductor and returns on the other. | balanced |
| The QPI link layer performs two key functions: flow control and | error control. |
| ___is a popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus. | The peripheral component interconnect (PCI) |
| The ___ function is needed to ensure that a sending QPI entity does not overwhelm a receiving QPI entity by sending data faster than the receiver can process the data and clear buffers for more incoming data. | flow control |
| ___ has a profound influence on both the organization of memory and on operating system memory management software. | Locality of reference |
| One assertion that locality is based on is that as a function of time, the probability that a given unit of memory is referenced tends to change... | slowly |
| ___ location reflects the tendency of a program to access data locations sequentially, such as when processing a table of data. | Spatial |
| For cache memory, ___ locality is traditionally exploited by keeping recently used instruction and data values in cache memory and by exploiting a cache hierarchy. | temporal |
| ___ locality is generally exploited by using larger cache blocks and by fetching items of anticipated use into the cache control logic | Spatial |
| ___ refers to when an instruction is fetched from a unit of memory, it is likely that in the near future additional instructions will be fetched from that same memory unit. | instruction temporal locality |
| ___ refers to when a data location is accessed, it is likely that in the near future additional instructions will be fetched from that same memory unit. | data temporal locality |
| The term ___ refers to whether memory is internal or external to the computer. | location |
| ___ memory consists of peripheral storage devices that are accessible to the processor via I/O controllers. | External |
| For main memory, ___ is the number of bits read out of or written into memory at a time. | Unit of transfer |
| ___ is a method of accessing units of data in which the access must be made in a specific linear sequence. | Sequential access |
| ___ is a random access type of memory that enables one to make a comparison of desired bit locations within a word for a specified match, and to do this for all words simultaneously. | Associative |
| For random access memory, ___ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. | Access time (latency) |
| ___ memory is the principal internal memory system of the computer. | Main |
| ___ is a design principle which means that copies of the same data unit in adjacent memory levels must be consistent | Coherence |
| External memory subsystems are accessible by the ___ via an I/O module. | processor |
| The principle of ___ reflects the observation that during the course of execution of a program memory references by the processor tend to cluster. | locality |
| Two forms of locality are temporal locality and | Spatial locality. |
| ___ locality refers to the tendency of a program to reference in the near future those units of memory referenced in the recent past. | Temporal |
| ___ locality refers to the tendency of a program to reference units of memory whose addresses are near to one another. | Spatial |
| ___instruction is an instruction that exists in the code to be executed. | Static |
| ___ instruction is instructions that appear in the execution trace of a program. | Dynamic |
| From a user's point of view, the two most important characteristics of memory are capacity and | performance |
| ___ is the rate at which data can be transferred into or out of a memory unit. | Transfer rate |
| ___ is a concept primarily applied to random-access memory and consists of the access time plus any additional time required before a second access can commence. | Memory cycle time |
| External, ___ is referred to as secondary memory or auxiliary memory. | nonvolatile memory |
| The three principles that guide the design of a memory hierarchy and the supporting memory management hardware and software are locality, inclusion, and | Coherence |
| ___ is the principle that makes effective use of a memory hierarchy possible. | Locality |
| For non-random-access memory, ___ (or latency) is the time it takes to position the read-write mechanism at the desired location. | Access time |
| The memory hierarchy design principle that dictates that all information items are originally stored in level Mn, where n is the level most remote from the processor is | Inclusion |
| The ___ cache is slower and typically larger than the L2 cache. | L3 |
| ___ is the minimum unit of transfer between cache and main memory. | Block |
| To distinguish between the data transferred and the chunk of physical memory, the term ___ , is sometimes used with reference to caches. | Frame |
| ___ is a portion of a cache line that is used for addressing purposes. | Line |
| The simplest technique for logically organizing cache is | Direct mapping |
| If a program happens to reference words repeatedly from two different blocks that map into the same line, the blocks will be continually swapped in the cache, and the hit ratio will be low, is a phenomenon known as | thrashing. |
| The principal disadvantage of ___ mapping is the complex circuitry required to examine the tags of all cache lines in parallel. | associative |
| The ___ replacement algorithm replaces the block in the set that has been in the cache longest with no reference to it. | least recently used (LRU) |
| ___ is easily implemented as a round-robin or circular buffer technique. | first-in-first-out (FIFO) |
| The ___ replacement algorithm replaces the block in the set that has been in the cache longest | first-in-first-out (FIFO) |
| The ___ dictates that a piece of data in one cache is guaranteed to be also found in all lower levels of caches. | inclusive policy |
| The ___ dictates that a piece of data in one cache is guaranteed not to be found in all lower levels of caches. | exclusive policy |
| The ___ fetches program instructions in order from the L2 cache, decodes these into a series of micro-operations, and stores the results in the L1 instruction cache. | Fetch/decode unit |
| The ___ execute micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers. | Execution units |
| With ___ additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches. | Hardware transparency |
| ___memory is designed to combine the memory access time of expensive, high-speed memory combined with the large memory size of less expensive, lower-speed memory. | cache |
| Because of the phenomenon of ___, when a block of data is fetched into the cache to satisfy a single memory reference, it is likely that there will be future references to that same memory location or to other words in the block. | Locality of reference |
| The term ___ refers to the number of data bytes, or block size, contained in a line. | line size |
| ___ computing deals with supercomputers and their software, especially for scientific applications that involve large amounts of data, vector and matrix computation, and the use of parallel algorithms. | High-performance computing (HPC) |
| A ___ cache stores data using main memory physical addresses. | physical |
| Three mapping techniques that are used for logically organizing cache are direct, ___ , and set-associative. | Fully Associative |
| ___ is constructed of static RAM cells but is considerably more expensive and holds much less data than regular SRAM chips. | Content-addressable memory (CAM) |
| ___ mapping is a compromise that exhibits the strengths of both the direct and associative approaches while reducing their disadvantages. | Set-associative |
| For set-associative mapping, the cache control logic interprets a memory address as three fields: Tag, ___, and Word. | Set |
| ___ is a replacement algorithm that replaces that block in the set that has experienced the fewest references. | least frequently used (LFU) |
| Three inclusion policies are found in contemporary cache systems: the inclusive policy, the ___, and the noninclusive policy. | exclusive policy |
| The Pentium 4 processor core consists of four major components: out-of-order execution logic, fetch/decode unit, execution units, and | Memory subsystem. |
| Using the ___ technique, all write operations are made to main memory as well as to the cache, ensuring that main memory is always. valid. | write through |
| A logical cache, also known as a virtual cache, stores data using ___ addresses. | virtual |
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