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DE_1.2Terms
DE_KeyTerms_Unit 1.2
Question | Answer |
---|---|
Instantaneous voltage of a waveform-maximum or peak or pulse | Amplitude |
Series of logic 1s and 0s plotted as a function of time | Digital Waveform |
Duty Cycle | Fraction of the total period that waveform is in the HIGH state. |
The part of the pulse that is in transition from HIGH to LOW | Falling Edge |
The numbers of cycles per unit of time | Frequency |
Unit of Frequency measured in cycles per second | Hertz |
The higher of the two voltages in a digital system. | Logic HIGH |
The lower of two voltages in a digital system. | Logic LOW |
A piece of electrical equipment used to view a variety of waveforms | Oscilloscope |
the amount of time measured in one complete cycle | Period |
Testing design function | Simulation |
Where amplitude varies in proportion to the sine function of an angle. | Sine Wave |
An almost instantaneous rise and decay of voltage or current in a periodic pattern. | Square Wave |
TTL-compatible IC that can be wired to operate in several different modes, such as a one-shot | 555 Timer |
An algebraic expression made up of Boolean variables and operators, such as AND (-), OR (+) or NOT (-). | Boolean Expression |
A type of flip-flop in which the D (data) input is the synchronous input. | Clocked D Flip-Flop |
One style of integrated circuit package which has two rows of leads | Dual In-Line Package (DIP) |
A sequential circuit based on a latch whose output changes when it's clock input receives a pulse. | Flip-Flop |
An electronic circuit having many components, such as transistors, diodes, resistors, and capacitors, in a single package. | Integrated Circuit (IC) |
Also called a NOT gate or an inverting buffer. | Invertor |
A diagram, similar to a schematic, showing the connection of logic gates. | Logic Diagram |
Delay from the time a signal is applied to the time when the output makes its change. | Propagation Delays |
A technique of entering CPLD design information by using a CAD tool to draw a logic circuit as a schematic. | Schematic Entry |