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Ch7-St1
Question | Answer |
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Burst EDO (BEDO) | is a newer EDO DRAM that is capable of processing four memory addresses in one burst. (BEDO) |
CAS Latency (CL) | is the delay time between the moment a memory controller tells the memory module to access a particular memory (CL) |
C-RIMM (Continuity RIMM) | is an inexpensive pass through module that allows for a continuous signal for computers with RIMM memory (Continuity RIMM) |
DDR2 | is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR2 |
DDR3 | is a modern kind of dynamic random access memory (DRAM) with a high bandwidth interface, and has been in use since DDR3 |
Direct Rambus DRAM | is a type of synchronous dynamic direct rambusDRAM |
Double Data Rate SDRAM | can theoretically improve memory access speed to at least 200 MHz Double Data Rate SDRAM |
DDR SDRAM | is a class of memory integrated circuits used in computers DDR SDRAM |
double-sided | documents from a computer with WINDOWS OS using the duplexer double sided |
dual channels | is being misused by some in the memory industry, which can mislead the consumer. The fact is there's no such thing as dual-channel memory dual channels |
dual ranked | is a set of DRAMs connected to the same chip select, and which are therefore accessed simultaneously dual ranked |
dynamic RAM (DRAM) | is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit dynamic |
ECC (error-correcting code) | are techniques that enable reliable delivery of digital data over unreliable communication channels ecc |
EDO (extended data out) | is a type of random access memory (RAM) chip that improves the time to read from memory on faster microprocessors such as the Intel Pentium edo |
FPM (fast page memory) | row access strobe (RAS) signal is kept active while the column access strobe (CAS) signal changes to read a sequence of contiguous memory cells fpm |